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    Delay-locked loop which includes a monitor to allow for proper alignment of signals
    2.
    发明授权
    Delay-locked loop which includes a monitor to allow for proper alignment of signals 失效
    延迟锁定环路，其包括监视器以允许信号的正确对准

    公开(公告)号：US06330296B1

    公开(公告)日：2001-12-11

    申请号：US09097130

    申请日：1998-06-12

    申请人： Francois Ibrahim Atallah ,  George Diniz ,  James Norris Dieffenderfer ,  David John Seman

    发明人： Francois Ibrahim Atallah ,  George Diniz ,  James Norris Dieffenderfer ,  David John Seman

    IPC分类号： H03D324

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/10

    摘要： The present invention provides a delay-locked loop (DLL). The DLL comprises a phase-frequency detector (PFD) for receiving a reference signal. The DLL further includes a charge pump which is coupled to the PFD. The DLL also includes a loop filter which is coupled to the charge pump and the PFD. Additionally in the DLL, delay line means is coupled to the charge pump and the loop filter. The delay line means provides a feedback signal to the PFD. The DLL further includes monitor means coupled to the PFD, the charge pump and the loop filter. The monitor means is for detecting when a voltage across the loop filter is at a predetermined level, wherein when the voltage is at the predetermined level the monitor means causes the PFD to enter a pump-down mode until the feedback signal is aligned with the reference signal. An advantage of the present invention is that DLL loop tracking failures based upon a stuck condition are reliably avoided. Specifically, the DLL in accordance with the present invention can reliably recover from the stuck condition in which the adjustable delay is at its lower limit and the PFD asserts the UP control signal. Additionally, the DLL is cost effective and is easily implemented utilizing existing processes.

    摘要翻译： 本发明提供一种延迟锁定环（DLL）。 该DLL包括用于接收参考信号的相位频率检测器（PFD）。 该DLL还包括耦合到PFD的电荷泵。 DLL还包括耦合到电荷泵和PFD的环路滤波器。 另外在DLL中，延迟线装置耦合到电荷泵和环路滤波器。 延迟线装置向PFD提供反馈信号。 DLL还包括耦合到PFD的监视器装置，电荷泵和环路滤波器。 监视器装置用于检测环路滤波器两端的电压何时处于预定电平，其中当电压处于预定电平时，监视装置使PFD进入降压模式，直到反馈信号与参考电压对齐 信号。 本发明的优点是可靠地避免了基于卡住状态的DLL循环跟踪故障。 具体地说，根据本发明的DLL可以可靠地从可调延迟处于其下限的停滞状态恢复，PFD断言UP控制信号。 此外，DLL是具有成本效益的，并且可以利用现有的过程容易地实现。

    Apparatus and methods to reduce castouts in a multi-level cache hierarchy
    5.
    发明授权
    Apparatus and methods to reduce castouts in a multi-level cache hierarchy 有权
    减少多级缓存层次结构中的丢弃的装置和方法

    公开(公告)号：US08078803B2

    公开(公告)日：2011-12-13

    申请号：US11669245

    申请日：2007-01-31

    申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

    摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.

    摘要翻译： 技术和方法用于控制从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于被确定为在下一级高速缓存中是冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而控制转储。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。

    Method and apparatus for segregating shared and non-shared data in cache memory banks
    6.
    发明授权
    Method and apparatus for segregating shared and non-shared data in cache memory banks 有权
    用于在高速缓存存储体中隔离共享和非共享数据的方法和装置

    公开(公告)号：US07353319B2

    公开(公告)日：2008-04-01

    申请号：US11144207

    申请日：2005-06-02

    申请人： Thomas Philip Speier ,  James Norris Dieffenderfer

    发明人： Thomas Philip Speier ,  James Norris Dieffenderfer

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0848 ,  G06F12/0831 ,  G06F12/0837 ,  Y02D10/13

    摘要： In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated for holding non-shared data. A non-shared data bank may be designated exclusively for holding non-shared data, so that shared data accesses do not interfere with non-shared accesses to that bank. Also, a shared data bank may be designated exclusively for holding shared data, and one or more banks may be designated for holding both shared and non-shared data. An access control circuit directs shared and non-shared accesses to respective banks based on receiving a shared indication signal in association with the accesses. Further, in one or more embodiments, the access control circuit reconfigures one or more bank designations responsive to a bank configuration signal.

    摘要翻译： 在多处理器系统中，控制对给定处理器的存储高速缓存的访问，使得共享数据访问被定向到指定用于保存共享数据的一个或多个库和/或非共享数据访问被定向到指定用于保存非共享数据的一个或多个库 共享数据。 非共享数据库可以专门用于保存非共享数据，使得共享数据访问不会干扰对该银行的非共享访问。 此外，共享数据库可以被专门用于保存共享数据，并且可以指定一个或多个存储体来保存共享和非共享数据。 访问控制电路基于接收与访问相关联的共享指示信号，将共享和非共享访问指向各个存储体。 此外，在一个或多个实施例中，访问控制电路响应于存储体配置信号重新配置一个或多个存储体指定。

    Method for filtering traffic to a physically-tagged data cache
    7.
    发明授权
    Method for filtering traffic to a physically-tagged data cache 有权
    将流量过滤到物理标记的数据高速缓存的方法

    公开(公告)号：US08612690B2

    公开(公告)日：2013-12-17

    申请号：US13426647

    申请日：2012-03-22

    申请人： Robert D. Clancy ,  James Norris Dieffenderfer ,  Thomas Philip Speier

    发明人： Robert D. Clancy ,  James Norris Dieffenderfer ,  Thomas Philip Speier

    IPC分类号： G06F12/10 ,  G06F7/04

    CPC分类号： G06F12/1054 ,  G06F12/0864 ,  G06F12/1045 ,  G06F12/1063 ,  Y02D10/13

    摘要： Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.

    摘要翻译： 公开了数据高速缓存的实施例，其提供了对数据高速缓存的物理标记的标签阵列的访问的数量的大量减少。 通常，数据高速缓存包括存储数据元素，物理标记的标签阵列和虚拟标记的标签阵列的数据阵列。 在一个实施例中，虚拟标记的标签阵列接收虚拟地址。 如果虚拟标记的标签阵列中的虚拟地址匹配，则虚拟标记的标签阵列将数据阵列中的虚拟地址标记在虚拟标记的数组中。 此外，在一个实施例中，虚拟标记的标签阵列禁用物理标记的标签阵列。 使用由虚拟标记的标签数组输出的方式，寻址数据数组中所需的数据元素。

    Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions
    9.
    发明申请
    Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions 有权
    在多个内存区域自动排序强顺序，设备和独占交易

    公开(公告)号：US20130151799A1

    公开(公告)日：2013-06-13

    申请号：US13315370

    申请日：2011-12-09

    申请人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

    发明人： Jason Lawrence Panavich ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Thomas Philip Speier

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1621

    摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.

    摘要翻译： 描述了用于控制弱订单存储系统中有序访问的高效技术。 存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。 需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。 在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。 对于保证完成的每个存储器请求，存储器访问计数器递减。 与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。 在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。

    Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy
    10.
    发明申请
    Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy 有权
    在多级缓存层次结构中减少铸件的装置和方法

    公开(公告)号：US20120059995A1

    公开(公告)日：2012-03-08

    申请号：US13292651

    申请日：2011-11-09

    申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

    摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.

    摘要翻译： 技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而减少了突发。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。 防止所选线路的分配节省与分配相关联的功率。