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21 条记录 (耗时 0.024 秒)

    External trace synchronization via periodic sampling
    1.
    发明授权
    External trace synchronization via periodic sampling 有权
    通过定期采样进行外部跟踪同步

    公开(公告)号：US08185879B2

    公开(公告)日：2012-05-22

    申请号：US11557005

    申请日：2006-11-06

    申请人： Radhika Thekkath ,  Franz Treue ,  Ernest L. Edgar ,  Richard T. Leatherman

    发明人： Radhika Thekkath ,  Franz Treue ,  Ernest L. Edgar ,  Richard T. Leatherman

    IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F11/00

    CPC分类号： G06F11/3636 ,  G06F11/3648 ,  G06F11/3656

    摘要： A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is completed. A trace record is formed during tracing. The trace record includes a processor mode indication, application space identity value and an instruction architecture set mode indication.

    摘要翻译： 用于跟踪多任务嵌入式流水线处理器的方法包括执行包括跟踪控制的编译代码。 执行编译代码时启动跟踪。 编译代码的执行完成后，跟踪停止。 在跟踪期间形成跟踪记录。 跟踪记录包括处理器模式指示，应用空间标识值和指令体系结构设置模式指示。

    Configurable co-processor interface
    4.
    发明授权
    Configurable co-processor interface 有权
    可配置的协处理器接口

    公开(公告)号：US07698533B2

    公开(公告)日：2010-04-13

    申请号：US11674924

    申请日：2007-02-14

    申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

    摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

    摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。

    Distributed tap controller
    6.
    发明授权
    Distributed tap controller 有权
    分布式龙头控制器

    公开(公告)号：US07231551B1

    公开(公告)日：2007-06-12

    申请号：US09894831

    申请日：2001-06-29

    申请人： Franz Treue ,  Lawrence Henry Hudepohl ,  Scott Michael McCoy ,  Radhika Thekkath

    发明人： Franz Treue ,  Lawrence Henry Hudepohl ,  Scott Michael McCoy ,  Radhika Thekkath

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3636

    摘要： A system accessible by a test access port controller via a test access port interface includes a data register. The data register is selectable based on an instruction register signal in the test access port interface. The instruction register signal is derived form an instruction register in the test access port controller. A shift register is connected to a data input and a data output in the test access port interface and to the data register. The operation of the shift register is controlled based on an indication of a state of a test access port controller state machine that is received over the test access port interface.

    摘要翻译： 由测试访问端口控制器通过测试访问端口接口访问的系统包括数据寄存器。 数据寄存器可以根据测试访问端口接口中的指令寄存器信号进行选择。 指令寄存器信号从测试访问端口控制器中的指令寄存器导出。 移位寄存器连接到测试访问端口接口和数据寄存器中的数据输入和数据输出。 基于通过测试访问端口接口接收的测试访问端口控制器状态机的状态的指示来控制移位寄存器的操作。

    Configurable out-of-order data transfer in a coprocessor interface
    7.
    发明授权
    Configurable out-of-order data transfer in a coprocessor interface 有权
    协处理器界面中可配置的无序数据传输

    公开(公告)号：US07237090B1

    公开(公告)日：2007-06-26

    申请号：US09751747

    申请日：2000-12-29

    申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    IPC分类号： G06F13/14

    CPC分类号： G06F9/3824 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3885

    摘要： An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors is provided. The interface includes an instruction bus and a data bus. The instruction bus is configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, where particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU. The data bus is configured to subsequently transfer the data. Data order signals within the data bus prescribe a data transfer order that differs from the instruction transfer order by prescribing a transfer corresponding to a specific outstanding particular instruction, where the data transfer order is relative to outstanding instructions. The outstanding instructions are those of the particular instructions transferred to the one of the plurality of coprocessors that have not completed a data transfer.

    摘要翻译： 提供了用于在中央处理单元（CPU）和多个协处理器之间传送数据的接口。 接口包括指令总线和数据总线。 指令总线被配置为以指令传送顺序将指令传送到多个协处理器，其中特定指令指示并引导多个协处理器中的一个将数据传送到/从CPU传送数据。 数据总线被配置为随后传送数据。 数据总线内的数据顺序信号通过规定与特定未完成特定指令相对应的传输，指定与指令传输顺序不同的数据传输顺序，其中数据传输顺序相对于未完成的指令。 未完成的指令是传送到尚未完成数据传送的多个协处理器之一的特定指令的指令。

    System and method for speeding up EJTAG block data transfers
    9.
    发明授权
    System and method for speeding up EJTAG block data transfers 有权
    用于加速EJTAG块数据传输的系统和方法

    公开(公告)号：US07065675B1

    公开(公告)日：2006-06-20

    申请号：US09850195

    申请日：2001-05-08

    申请人： Radhika Thekkath ,  Scott Michael McCoy ,  Franz Treue ,  Morten Zilmer ,  G. Michael Uhler

    发明人： Radhika Thekkath ,  Scott Michael McCoy ,  Franz Treue ,  Morten Zilmer ,  G. Michael Uhler

    IPC分类号： G06F11/00

    CPC分类号： G01R31/318544 ,  G01R31/31705

    摘要： A system and method for providing efficient block transfer operations through a test access port uses a Fastdata register. The Fastdata register, in part, emulates a pending process access bit (“PrAcc”) typically found in a Control register associated with the test access port. When a Fastdata access (either a Fastdata upload or a Fastdata download) is requested by a probe coupled to the test access port, the Fastdata register is serially coupled to a data register also associated with the test access port. With these registers so coupled and through the operation of the Fastdata register, downloading and uploading data can be accomplished using a single register operation.

    摘要翻译： 通过测试访问端口提供有效的块传输操作的系统和方法使用Fastdata寄存器。 Fastdata寄存器部分地模拟通常在与测试访问端口相关联的控制寄存器中找到的待处理进程访问位（“PrAcc”）。 当FastData访问（Fastdata上传或Fastdata下载）被耦合到测试访问端口的探测器请求时，Fastdata寄存器串行耦合到也与测试访问端口相关联的数据寄存器。 通过这些寄存器如此耦合，并通过Fastdata寄存器的操作，可以使用单个寄存器操作来完成下载和上传数据。

    Configurable co-processor interface
    10.
    发明授权
    Configurable co-processor interface 有权
    可配置的协处理器接口

    公开(公告)号：US07886129B2

    公开(公告)日：2011-02-08

    申请号：US10923584

    申请日：2004-08-20

    申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

    摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

    摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。