公开(公告)号：US06647362B1

公开(公告)日：2003-11-11

申请号：US09405602

申请日：1999-09-24

申请人： Frederic Reblewski ,  Jean Barbier ,  Olivier Lepape

发明人： Frederic Reblewski ,  Jean Barbier ,  Olivier Lepape

IPC分类号： G06F9455

CPC分类号： G06F17/5027

摘要： A scalable emulation system is disclosed. The basic embodiment of the emulation system includes a number of logic boards with logic chips that are reconfigurable to emulate circuit elements of a circuit design. The basic embodiment further includes a number of interconnect boards coupled to at least the logic boards. Each of the interconnect boards includes interconnect chips that are reconfigurable to selectively interconnect the logic chips of different ones of the logic boards. Additionally, at least each of a subset of the interconnect boards includes a number of expansion connectors for facilitating expansion of the emulation system in one or more selected ones of expansion orientations through coupling of at least one or more substantial replicates of the basic embodiment.

摘要翻译： 公开了一种可扩展的仿真系统。 仿真系统的基本实施例包括具有逻辑芯片的多个逻辑板，其可重构以仿真电路设计的电路元件。 基本实施例还包括耦合到至少逻辑板的多个互连板。 每个互连板包括互连芯片，其可重新配置以选择性地互连不同逻辑板的逻辑芯片。 此外，互连板的子集中的至少每一个包括多个扩展连接器，用于通过耦合基本实施例的至少一个或多个基本重复来促进仿真系统在一个或多个选定扩展方向中的扩展。

公开(公告)号：US6057706A

公开(公告)日：2000-05-02

申请号：US985372

申请日：1997-12-04

申请人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

IPC分类号： G01R31/317 ,  H03K19/177

CPC分类号： G01R31/31705 ,  G01R31/318519 ,  G01R31/318544 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17748 ,  H03K19/17764 ,  H03K19/17772

摘要： A number of enhanced logic elements (LEs) are provided to form a FPGA. Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved FPGA further comprises a network of crossbars, a context bus, a scan register, and a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated. Furthermore, the enhanced LEs may be used for "level sensitive" as well as "edge sensitive" circuit design emulations.

摘要翻译： 提供了许多增强型逻辑元件（LE）来形成FPGA。 每个增强LE包括多输入单输出真值表，以及具有数据，集合和复位输入的互补对主控从锁存器。 每个增强型LE还包括多个复用器和缓冲器以及控制逻辑。 此外，改进的FPGA还包括交叉开关网络，上下文总线，扫描寄存器和多个触发电路。 结果，每个LE可以被单独初始化，其信号状态暂时冻结，冻结状态被读取，跟踪数据被输出，并且有条件地产生触发输入。 此外，增强型LE可用于“电平敏感”以及“边缘敏感”电路设计仿真。

公开(公告)号：US07098688B2

公开(公告)日：2006-08-29

申请号：US10668236

申请日：2003-09-24

申请人： Frederic Reblewski ,  Olivier LePape ,  Jean Barbier

发明人： Frederic Reblewski ,  Olivier LePape ,  Jean Barbier

IPC分类号： H03K19/177

CPC分类号： G06F17/5027

摘要： A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.

摘要翻译： 区域时间复用仿真系统包括用于仿真电路设计的仿真器。 仿真器包括具有缓冲I / O引脚和可重配置逻辑元件的多个可重新配置的逻辑器件。 可重配置逻辑器件可重新配置以使用至少一个用户时钟来模拟电路设计来对逻辑元件进行时钟以及至少一个信号路由时钟以将可重构逻辑器件之间的仿真信号的路由与该至少一个信号路由 时钟独立于至少一个用户时钟。

公开(公告)号：US5907697A

公开(公告)日：1999-05-25

申请号：US688329

申请日：1996-07-30

申请人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

IPC分类号： H03K19/177 ,  G06F9/455

CPC分类号： G06F15/7867

摘要： A scalable multi-level multi-stage network topology is employed to interconnect reconfigurable logic elements within the special purpose FPGA, inter-FPGA, inter-logic boards, and inter-backplanes. More specifically, under the presently preferred embodiment, an on-chip 3-stage inter-logic element crossbar network is provided to each special purpose FPGA for interconnecting the reconfigurable logic elements and the I/O pins of the special purpose FPGA. A two level three-stage inter-FPGA hybrid crossbar network is provided to interconnect the special purpose FPGAs and I/O pins of the logic board. The two-level three-stage inter-FPGA hybrid crossbar network consists of two stages of programmable crossbars and one stage of one or more special purpose FPGAs used for interconnection only. The exact number of special purpose FPGAs to be used for interconnection only on a particular logic board is dependent on the specific circuit design being emulated. A two-level two-stage inter-board crossbar network is provided to interconnect the logic boards or I/O boards for interconnecting the logic elements to external devices. Finally, a single-stage inter-backplane network and a number of PCBs are provided to interconnect multi-backplanes to form a multi-crate system.

摘要翻译： 采用可扩展的多级多级网络拓扑来互连专用FPGA，FPGA间，逻辑间板以及内插板之间的可重构逻辑元件。 更具体地说，在目前优选的实施例中，为每个专用FPGA提供了一个片上3级跨逻辑元件交叉网络，用于互连可重配置逻辑元件和专用FPGA的I / O引脚。 提供了两级三级FPGA间混合交叉网络，以互连逻辑板的专用FPGA和I / O引脚。 两级三级FPGA间混合交叉网络由两段可编程交叉开关组成，一级用于仅用于互连的一个或多个特殊用途FPGA。 仅在特定逻辑板上用于互连的专用FPGA的确切数量取决于正在仿真的具体电路设计。 提供两级两级跨板交叉网络来互连逻辑板或I / O板，用于将逻辑元件互连到外部设备。 最后，提供单级背板间网络和多个PCB以便互连多个背板以形成多箱体系统。

公开(公告)号：US5777489A

公开(公告)日：1998-07-07

申请号：US542838

申请日：1995-10-13

申请人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

IPC分类号： G01R31/317 ,  H03K19/177

CPC分类号： G01R31/31705 ,  G01R31/318519 ,  G01R31/318544 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17748 ,  H03K19/17764 ,  H03K19/17772

摘要： A number of enhanced logic elements (LEs) are provided to form a FPGA. Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved FPGA further comprises a network of crossbars, a context bus, a scan register, and a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated. Furthermore, the enhanced LEs may be used for "level sensitive" as well as "edge sensitive" circuit design emulations.

公开(公告)号：US5754827A

公开(公告)日：1998-05-19

申请号：US542946

申请日：1995-10-13

申请人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

IPC分类号： G01R31/3185 ,  G06F11/26 ,  G06F11/36 ,  H03K19/177

CPC分类号： G06F11/3636 ,  G01R31/318591 ,  G06F11/261

摘要： An emulation system is constituted with a plurality of FPGAs having on-chip integrated debugging facilities, distributively disposed on a plurality of circuit boards. Each FPGA's on-chip integrated debugging facilities include in particular, a scan register for outputting trace data, and comparison circuitry for generating inputs for a plurality of system triggers. Correspondingly, each board is provided with a plurality of trace memory for recording the trace data, and summing circuitry for generating partial sums for the triggers. The relative memory location within a clock cycle of trace data where the output of a LE will be recorded is predeterminable. Additionally, a system sync memory is provided for storing a plurality of sync patterns to facilitate reconstitution of trace data of a trace session. Lastly, the compilation or mapping software is enhanced to generate a cross-reference file cross referencing each circuit element in a circuit design to the predeterminable relative memory location within a clock cycle of trace data where the trace data for the particular circuit element can be found. Together, these elements allow fully visible tracing to be performed for an emulation.

摘要翻译： 仿真系统由具有片上集成调试设备的多个FPGA构成，分布式布置在多个电路板上。 每个FPGA的片上集成调试功能特别包括用于输出跟踪数据的扫描寄存器和用于生成用于多个系统触发的输入的比较电路。 相应地，每个板设置有用于记录跟踪数据的多个跟踪存储器，以及用于为触发产生部分和的求和电路。 跟踪数据的时钟周期内的相对存储器位置，其中将记录LE的输出将被预先确定。 另外，系统同步存储器被提供用于存储多个同步模式以便于重建跟踪会话的跟踪数据。 最后，增强编译或映射软件以产生交叉参考文件，将交叉参考文件交叉参考电路设计中的每个电路元件到跟踪数据的时钟周期内的可预定的相对存储器位置，其中可以找到特定电路元件的跟踪数据 。 一起，这些元素允许为仿真执行完全可见的跟踪。

公开(公告)号：US5574388A

公开(公告)日：1996-11-12

申请号：US542519

申请日：1995-10-13

申请人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

IPC分类号： H03K19/177

CPC分类号： G06F15/7867

摘要： A scalable multi-level multi-stage network topology is employed to interconnect reconfigurable logic elements within the FPGA, inter-FPGA, interlogic boards, and inter-backplanes. More specifically, under the presently preferred embodiemnt, an on-chip 3-stage inter-logic element crossbar network is provided to each FPGA for interconnecting the reconfigurable logic elements and the I/O pins of the FPGA. A two level two-stage inter-FPGA crossbard network is provided to interconnect the FPGAs and I/O pins of the logic board. A two-level two-stage inter-board crossbar network is provided to interconnect the logic boards or I/O boards for interconnecting the logic elements to external devices. Finally, a single-stage inter-backplane network and a number of PCBs are provided to interconnect multi-backplanes to form a multi-crate system.

摘要翻译： 采用可扩展的多级多级网络拓扑来互连FPGA，FPGA，内部板和内插板之间的可重配置逻辑元件。 更具体地，在目前优选的实施例中，向每个FPGA提供片上3级跨逻辑元件交叉网络，用于互连可重构逻辑元件和FPGA的I / O引脚。 提供了两级两级FPGA间交叉网络，用于互连逻辑板的FPGA和I / O引脚。 提供两级两级跨板交叉网络来互连逻辑板或I / O板，用于将逻辑元件互连到外部设备。 最后，提供单级背板间网络和多个PCB以便互连多个背板以形成多箱体系统。

公开(公告)号：US5790832A

公开(公告)日：1998-08-04

申请号：US639248

申请日：1996-04-23

申请人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5027

摘要： A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence identifies how values of the hidden nodes are to be determined based on corresponding ones of the physically observable nodes. The value of a hidden node is determined by obtaining the values of the corresponding physically observable nodes and identifying the value of the hidden node based on the correspondence between the corresponding physically observable nodes and the hidden node.

摘要翻译： 用于跟踪仿真器中的任何节点（包括电路设计的隐藏节点）的方法和装置包括维持被仿真的电路设计的物理可观察节点和隐藏节点之间的对应关系。 该对应关系确定隐藏节点的值是如何根据物理上可观察到的节点中的相应节点确定的。 通过获得相应的物理可观察节点的值并根据相应的物理可观察节点和隐藏节点之间的对应关系来识别隐藏节点的值来确定隐藏节点的值。

公开(公告)号：US06717433B2

公开(公告)日：2004-04-06

申请号：US10086813

申请日：2002-02-28

申请人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

IPC分类号： H03K1900

CPC分类号： G01R31/31705 ,  G01R31/318519 ,  G01R31/318544 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17748 ,  H03K19/17764 ,  H03K19/17772

摘要： A number of enhanced logic elements (LEs) are provided to form a reconfigurable integrated circuit (IC). Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved IC may further comprises a scalable network of crossbars, a context bus, a scan register, and/or a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated, making the IC particularly suitable for circuit design emulation. Furthermore, the enhanced LEs may be used for “level sensitive” as well as “edge sensitive” circuit design emulations.

摘要翻译： 提供了许多增强型逻辑元件（LE）以形成可重构集成电路（IC）。 每个增强LE包括多输入单输出真值表，以及具有数据，集合和复位输入的互补对主控从锁存器。 每个增强型LE还包括多个复用器和缓冲器以及控制逻辑。 此外，改进的IC还可以包括交叉开关的可伸缩网络，上下文总线，扫描寄存器和/或多个触发电路。 结果，每个LE可以单独初始化，其信号状态瞬间冻结，读取冻结状态，输出跟踪数据，有条件地产生触发输入，使得IC特别适用于电路设计仿真。 此外，增强型LE可用于“电平敏感”以及“边缘敏感”电路设计仿真。

公开(公告)号：US06388465B1

公开(公告)日：2002-05-14

申请号：US09525210

申请日：2000-03-14

申请人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

发明人： Jean Barbier ,  Olivier LePape ,  Frederic Reblewski

IPC分类号： H03K19177

CPC分类号： G01R31/31705 ,  G01R31/318519 ,  G01R31/318544 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17748 ,  H03K19/17764 ,  H03K19/17772

摘要： A number of enhanced logic elements (LEs) are provided to form a [FPGA] reconfigurable integrated circuit (IC). Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved [FPGA] IC may further comprise[s] a scalable network of crossbars, a context bus, a scan register, and/or a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated, making the IC particularly suitable for circuit design emulation. Furthermore, the enhanced LEs may be used for “level sensitive” as well as “edge sensitive” circuit design emulations.

摘要翻译： 提供了许多增强型逻辑元件（LE）来形成[FPGA]可重构集成电路（IC）。 每个增强LE包括多输入单输出真值表，以及具有数据，集合和复位输入的互补对主控从锁存器。 每个增强型LE还包括多个复用器和缓冲器以及控制逻辑。 此外，改进的[FPGA] IC还可以包括可伸缩网络的交叉开关，上下文总线，扫描寄存器和/或多个触发电路。 结果，每个LE可以单独初始化，其信号状态瞬间冻结，读取冻结状态，输出跟踪数据，有条件地产生触发输入，使得IC特别适用于电路设计仿真。 此外，增强型LE可用于“电平敏感”以及“边缘敏感”电路设计仿真。