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    Emulation system scaling
    1.
    发明授权
    Emulation system scaling 有权
    仿真系统缩放

    公开(公告)号：US06647362B1

    公开(公告)日：2003-11-11

    申请号：US09405602

    申请日：1999-09-24

    申请人： Frederic Reblewski ,  Jean Barbier ,  Olivier Lepape

    发明人： Frederic Reblewski ,  Jean Barbier ,  Olivier Lepape

    IPC分类号： G06F9455

    CPC分类号： G06F17/5027

    摘要： A scalable emulation system is disclosed. The basic embodiment of the emulation system includes a number of logic boards with logic chips that are reconfigurable to emulate circuit elements of a circuit design. The basic embodiment further includes a number of interconnect boards coupled to at least the logic boards. Each of the interconnect boards includes interconnect chips that are reconfigurable to selectively interconnect the logic chips of different ones of the logic boards. Additionally, at least each of a subset of the interconnect boards includes a number of expansion connectors for facilitating expansion of the emulation system in one or more selected ones of expansion orientations through coupling of at least one or more substantial replicates of the basic embodiment.

    摘要翻译： 公开了一种可扩展的仿真系统。 仿真系统的基本实施例包括具有逻辑芯片的多个逻辑板，其可重构以仿真电路设计的电路元件。 基本实施例还包括耦合到至少逻辑板的多个互连板。 每个互连板包括互连芯片，其可重新配置以选择性地互连不同逻辑板的逻辑芯片。 此外，互连板的子集中的至少每一个包括多个扩展连接器，用于通过耦合基本实施例的至少一个或多个基本重复来促进仿真系统在一个或多个选定扩展方向中的扩展。

    Method and apparatus for tracing any node of an emulation
    2.
    发明授权
    Method and apparatus for tracing any node of an emulation 失效
    用于跟踪仿真的任何节点的方法和装置

    公开(公告)号：US5790832A

    公开(公告)日：1998-08-04

    申请号：US639248

    申请日：1996-04-23

    申请人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

    发明人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5027

    摘要： A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence identifies how values of the hidden nodes are to be determined based on corresponding ones of the physically observable nodes. The value of a hidden node is determined by obtaining the values of the corresponding physically observable nodes and identifying the value of the hidden node based on the correspondence between the corresponding physically observable nodes and the hidden node.

    摘要翻译： 用于跟踪仿真器中的任何节点（包括电路设计的隐藏节点）的方法和装置包括维持被仿真的电路设计的物理可观察节点和隐藏节点之间的对应关系。 该对应关系确定隐藏节点的值是如何根据物理上可观察到的节点中的相应节点确定的。 通过获得相应的物理可观察节点的值并根据相应的物理可观察节点和隐藏节点之间的对应关系来识别隐藏节点的值来确定隐藏节点的值。

    Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network
    3.
    发明授权
    Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network 失效
    仿真系统具有可扩展的多级多级混合可编程互连网络

    公开(公告)号：US5907697A

    公开(公告)日：1999-05-25

    申请号：US688329

    申请日：1996-07-30

    申请人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

    发明人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

    IPC分类号： H03K19/177 ,  G06F9/455

    CPC分类号： G06F15/7867

    摘要： A scalable multi-level multi-stage network topology is employed to interconnect reconfigurable logic elements within the special purpose FPGA, inter-FPGA, inter-logic boards, and inter-backplanes. More specifically, under the presently preferred embodiment, an on-chip 3-stage inter-logic element crossbar network is provided to each special purpose FPGA for interconnecting the reconfigurable logic elements and the I/O pins of the special purpose FPGA. A two level three-stage inter-FPGA hybrid crossbar network is provided to interconnect the special purpose FPGAs and I/O pins of the logic board. The two-level three-stage inter-FPGA hybrid crossbar network consists of two stages of programmable crossbars and one stage of one or more special purpose FPGAs used for interconnection only. The exact number of special purpose FPGAs to be used for interconnection only on a particular logic board is dependent on the specific circuit design being emulated. A two-level two-stage inter-board crossbar network is provided to interconnect the logic boards or I/O boards for interconnecting the logic elements to external devices. Finally, a single-stage inter-backplane network and a number of PCBs are provided to interconnect multi-backplanes to form a multi-crate system.

    摘要翻译： 采用可扩展的多级多级网络拓扑来互连专用FPGA，FPGA间，逻辑间板以及内插板之间的可重构逻辑元件。 更具体地说，在目前优选的实施例中，为每个专用FPGA提供了一个片上3级跨逻辑元件交叉网络，用于互连可重配置逻辑元件和专用FPGA的I / O引脚。 提供了两级三级FPGA间混合交叉网络，以互连逻辑板的专用FPGA和I / O引脚。 两级三级FPGA间混合交叉网络由两段可编程交叉开关组成，一级用于仅用于互连的一个或多个特殊用途FPGA。 仅在特定逻辑板上用于互连的专用FPGA的确切数量取决于正在仿真的具体电路设计。 提供两级两级跨板交叉网络来互连逻辑板或I / O板，用于将逻辑元件互连到外部设备。 最后，提供单级背板间网络和多个PCB以便互连多个背板以形成多箱体系统。

    Method and apparatus tracing any node of an emulation
    4.
    发明授权
    Method and apparatus tracing any node of an emulation 失效
    跟踪仿真的任何节点的方法和设备

    公开(公告)号：US5999725A

    公开(公告)日：1999-12-07

    申请号：US62240

    申请日：1998-04-17

    申请人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

    发明人： Jean Barbier ,  Olivier Lepape ,  Frederic Reblewski

    IPC分类号： G06F11/26 ,  G06F19/00

    CPC分类号： G06F11/261

    摘要： A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence identifies how values of the hidden nodes are to be determined based on corresponding ones of the physically observable nodes. The value of a hidden node is determined by obtaining the values of the corresponding physically observable nodes and identifying the value of the hidden node based on the correspondence between the corresponding physically observable nodes and the hidden node.

    摘要翻译： 用于跟踪仿真器中的任何节点（包括电路设计的隐藏节点）的方法和装置包括维持被仿真的电路设计的物理可观察节点和隐藏节点之间的对应关系。 该对应关系确定隐藏节点的值是如何根据物理上可观察到的节点中的相应节点确定的。 通过获得相应的物理可观察节点的值并根据相应的物理可观察节点和隐藏节点之间的对应关系来识别隐藏节点的值来确定隐藏节点的值。

    Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits
    5.
    发明授权
    Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits 有权
    具有降低的寄生电容负载和可重构电路中交叉开关器件的使用的交叉开关器件

    公开(公告)号：US06874136B2

    公开(公告)日：2005-03-29

    申请号：US10043964

    申请日：2002-01-10

    申请人： Frederic Reblewski ,  Olivier Lepape

    发明人： Frederic Reblewski ,  Olivier Lepape

    IPC分类号： H03K17/16 ,  H03K17/693 ,  G06F17/50 ,  G06F9/45

    CPC分类号： H03K17/693 ,  H03K17/162

    摘要： A crossbar device includes a first set of input lines and a second set of output lines. A plurality of chains of pass transistors are provided to selectively couple the input lines to the output lines in a reduced parasitic capacitive loading manner. Further, memory elements and decoder logic are provided to facilitate control of the selective coupling. Additionally, a low power application of multiple crossbar devices to a reconfigurable circuit block is improved by having each memory element of a crossbar device be provided with a supply voltage higher by a Vth to maintain the input voltage of corresponding output buffers at Vdd. Further, an application of multiple crossbar devices to a reconfigurable circuit block is improved by coupling a control circuitry via a control line to all output buffers of the interconnected crossbar devices to force the output buffers to a known state at power-on.

    摘要翻译： 横杆装置包括第一组输入线和第二组输出线。 提供多个传送晶体管链，以便以减小的寄生电容负载方式选择性地将输入线耦合到输出线。 此外，提供存储器元件和解码器逻辑以便于选择性耦合的控制。 此外，通过使交叉开关器件的每个存储器元件具有高于Vth的电源电压以将相应的输出缓冲器的输入电压维持在Vdd来提高多个交叉开关器件对可重构电路块的低功率应用。 此外，通过经由控制线将控制电路耦合到互连的交叉开关器件的所有输出缓冲器来将多个交叉开关器件应用于可重新配置的电路块得到改善，以在上电时迫使输出缓冲器处于已知状态。

    Reconfigurable integrated circuit with integrated debugging facilities for use in an emulation system
    7.
    发明授权
    Reconfigurable integrated circuit with integrated debugging facilities for use in an emulation system 有权
    具有集成调试功能的可重构集成电路，用于仿真系统

    公开(公告)号：US06265894B1

    公开(公告)日：2001-07-24

    申请号：US09404925

    申请日：1999-09-24

    申请人： Frederic Reblewski ,  Olivier Lepape

    发明人： Frederic Reblewski ,  Olivier Lepape

    IPC分类号： H03K19177

    CPC分类号： G06F11/261 ,  G01R31/31705 ,  G01R31/318516 ,  G01R31/318552 ,  H03K19/17728 ,  H03K19/17764

    摘要： An integrated circuit is described as comprising a plurality of logic elements (LEs), each of which having a plurality of outputs, and a partial scan register. The plurality of LEs are operative to generate a plurality of output signals in response to a plurality of input signals correspondingly applied to the LEs. The partial scan register is reconfigurably coupled to select ones of the LEs such that, when enabled, the partial scan register is operative to capture and output on a scan bus a record of signal state values circuit elements emulated by the selected LEs in a particular clock cycle of an operating clock, wherein the partial scan register is enabled with application of a scan clock appropriately scaled to the operating clock.

    摘要翻译： 集成电路被描述为包括多个逻辑元件（LE），每个逻辑元件具有多个输出，以及部分扫描寄存器。 响应于对应于LE的多个输入信号，多个LE可操作地产生多个输出信号。 部分扫描寄存器被可重新配置地耦合以选择LE中的一个，使得当使能时，部分扫描寄存器可操作以在扫描总线上捕获和输出信号状态值的记录由特定时钟中的所选LE仿真的电路元件 操作时钟的周期，其中通过应用适当地缩放到操作时钟的扫描时钟来启用部分扫描寄存器。

    Reconfigurable integrated circuit with a scalable architecture
    9.
    发明授权
    Reconfigurable integrated circuit with a scalable architecture 有权
    具有可扩展架构的可重构集成电路

    公开(公告)号：US06594810B1

    公开(公告)日：2003-07-15

    申请号：US09971349

    申请日：2001-10-04

    申请人： Frederic Reblewski ,  Olivier Lepape

    发明人： Frederic Reblewski ,  Olivier Lepape

    IPC分类号： G06F1750

    CPC分类号： H04Q3/68 ,  G06F15/7867 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13109 ,  H04Q2213/13322

    摘要： An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

    摘要翻译： 集成电路（IC）包括多个功能块（FB），其中至少一个可重新配置。 每个FB可以是可重新配置的功能或不可重新配置的功能，或者用附加的“嵌套”功能块递归地展开。 IC还包括多个输入引脚，多个输出引脚和多个交叉开关器件。 至少在IC级别的元件以这样的方式耦合，使得所有输入信号通过交叉开关器件的第一子集提供给FB，所有内部信号通过第二子集的第二子集从一个FB路由到另一个FB 交叉开关器件，并且所有输出信号通过第三子交叉开关器件从FB路由到输出引脚。 为了提高路由性和速度，每个交叉开关设备输出都有一个扇出。 另外，每个横杠装置可以仅向每个其他横杆装置提供一个输入。