公开(公告)号：USRE37419E1

公开(公告)日：2001-10-23

申请号：US09430060

申请日：1999-10-29

申请人： Fu-Change Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

发明人： Fu-Change Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

IPC分类号： G11C1604

CPC分类号： G11C11/5621 ,  G11C8/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3445 ,  G11C2211/5621 ,  H01L27/115

摘要： A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and a verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.

摘要翻译： 闪存电路包括具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器。 字线解码器和源极线解码器提供同时擦除闪存中的两个相邻字线的存储单元的能力，并且逐字地验证存储单元字。 通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关的过度擦除和源干扰问题。 解码架构提供了可能从一对到大量多对字线的灵活的擦除大小。 通过将字线的存储单元划分成多个段并具有由源段控制线和晶体管控制的分段源极线，解码电路还提供选择用于擦除的字线段的存储单元的能力。 对于源段控制线和晶体管以及字线的布局提出了几种不同的方法。