Data processing system having pipeline arithmetic/logic units
    2.
    发明授权
    Data processing system having pipeline arithmetic/logic units 失效
    数据处理系统具有流水线算术/逻辑单元

    公开(公告)号:US4783783A

    公开(公告)日:1988-11-08

    申请号:US888936

    申请日:1986-07-24

    摘要: A data processing system includes a multistage pipeline arithmetic/logic operation unit for implementing an arithmetic or logic operation for sets of element data sequentially and storing operational results sequentially in a memory using a single instruction. Check information indicative of the presence or absence of a fault occurring in each stage of the pipeline operation unit is moved in synchronism with the advancement of stages of the pipeline operation unit. A request control unit for storing the operational result in the memory suppresses the storing of the operational result in the memory if check information indicates a fault of the operational result which is being stored in the memory. The request control unit issues storage requests, which are counted by a counter. The counter indicates the number of elements stored normally in the memory.

    摘要翻译: 一种数据处理系统包括:多级流水线运算/逻辑运算单元,用于依次执行元件数据集的运算或逻辑运算,并使用单个指令将运算结果顺序存储在存储器中。 与流水线操作单元的各级的前进同步地移动表示流水线操作单元的各个阶段中出现故障的存在或不存在的信息。 如果检查信息指示存储在存储器中的操作结果的故障,则将存储操作结果存储在存储器中的请求控制单元禁止将操作结果存储在存储器中。 请求控制单元发出由计数器计数的存储请求。 计数器指示存储器中正常存储的元素数量。

    Vector data buffer and method of reading data items from a banked
storage without changing the data sequence thereof
    3.
    发明授权
    Vector data buffer and method of reading data items from a banked storage without changing the data sequence thereof 失效
    向量数据缓冲器和从存储的存储器读取数据项而不改变其数据序列的方法

    公开(公告)号:US5497467A

    公开(公告)日:1996-03-05

    申请号:US742832

    申请日:1991-08-08

    CPC分类号: G06F15/8084 G06F5/065

    摘要: A vector data processor includes a vector data buffer for receiving a plurality of arrayed data items requested from a storage including a plurality of storage banks (banks-0-3 in FIG. 2) for independent operations. The vector data buffer is constructed of a plurality of bank memories which conform to a corresponding periodic relationship between the arrayed data items and the storage banks. Date storing areas for storing the arrayed data items are preset on the successively different bank memories of the vector data buffer in the sequence in which the individual arrayed data items have been requested. The individual storage banks in the sequence in which the arrayed data items have been requested are respectively connected to the successively different bank memories, and the arrayed data items fetched from the individual storing banks are stored in the connected bank memories in succession.

    摘要翻译: 矢量数据处理器包括一个矢量数据缓冲器,用于从用于独立操作的多个存储体(图2中的组-0-3)的存储器接收从多个存储器请求的多个阵列数据项目。 矢量数据缓冲器由符合排列的数据项和存储库之间的对应的周期关系的多个存储体构成。 用于存储阵列数据项的日期存储区域在已经请求了各个排列的数据项的顺序中预设在向量数据缓冲器的连续不同的存储体中。 已经请求排列的数据项的序列中的各个存储体分别连接到连续不同的存储体存储器,并且从各个存储库取出的排列的数据项被连续地存储在连接的存储体存储器中。

    Method of accessing multiple virtual address spaces and computer system
    4.
    发明授权
    Method of accessing multiple virtual address spaces and computer system 失效
    访问多个虚拟地址空间和计算机系统的方法

    公开(公告)号:US5295251A

    公开(公告)日:1994-03-15

    申请号:US585973

    申请日:1990-09-21

    IPC分类号: G06F12/10 G06F12/00

    CPC分类号: G06F12/1036

    摘要: A computer system operable as a virtual machine system capable of accessing multiple virtual address spaces, which has an access register translation means for translating a space identifier into an origin address of a table for address translation and a translation pair memory for storing translation pairs of the space identifiers and the associated origin addresses. In each entry of the translation pair memory, a field is provided in association with the translation pair, for storing a machine identifier of the guest virtual machine associated with the translation pair. When accessing a virtual address space, a guest virtual machine makes reference only to the associated translation pair based on the virtual machine identifier thereof.

    摘要翻译: 一种可操作为能够访问多个虚拟地址空间的虚拟机系统的计算机系统,其具有用于将空间标识符转换为用于地址转换的表的原始地址的访问寄存器转换装置,以及用于存储翻译对的翻译对存储器 空格标识符和相关的起始地址。 在翻译对存储器的每个条目中,提供与翻译对相关联的字段,用于存储与翻译对相关联的客户虚拟机的机器标识符。 当访问虚拟地址空间时,来宾虚拟机仅基于其虚拟机标识符仅引用相关联的转换对。

    Agricultural or horticultural preparation with light stability
    5.
    发明授权
    Agricultural or horticultural preparation with light stability 失效
    具有光稳定性的农业或园艺制剂

    公开(公告)号:US06242383B1

    公开(公告)日:2001-06-05

    申请号:US09486539

    申请日:2000-02-29

    IPC分类号: A01N4302

    摘要: An object of the present invention is to provide an agricultural/horticultural preparation having improved photostability, comprising MK 8383 substance. A composition according to the present invention comprises a compound of formula (I): wherein R1 represents hydrogen atom, or a lower alkyl or alkyl carbonyl group, and R2 represents hydroxyl group or a lower alkoxy group, or its salt, and cyclodextrins.

    摘要翻译: 本发明的目的是提供具有改善的光稳定性的农业/园艺制剂,其包含MK 8383物质。 根据本发明的组合物包含式(I)化合物:其中R 1表示氢原子,或低级烷基或烷基羰基,R 2表示羟基或低级烷氧基,或其盐和环糊精。

    Guest execution control system, method and computer process for a
virtual machine system
    6.
    发明授权
    Guest execution control system, method and computer process for a virtual machine system 失效
    客户执行控制系统,虚拟机系统的方法和计算机进程

    公开(公告)号:US5813039A

    公开(公告)日:1998-09-22

    申请号:US566177

    申请日:1995-12-01

    申请人: Fujio Wakui

    发明人: Fujio Wakui

    CPC分类号: G06F9/45533

    摘要: A guest execution control system method and computer process for a virtual machine system having a main storage for holding a state descriptor of a guest virtual machine, and a plurality of instruction processors each starting execution of the guest virtual machine by executing an execution start instruction for the guest virtual machine. Execution instruction information in the state descriptor indicating whether execution of the guest virtual machine is to be finished is changed when a state of the virtual machine satisfies a predetermined condition during execution of the guest virtual machine. The execution instruction information is held at an address in the main storage. The guest execution control system includes a circuit which compares an address in the main storage of information being changed with the address in the main storage of the execution instruction information, and informs the guest virtual machine being executed that the execution instruction information has been changed when the address in the main storage of information being changed is the same as the address in the main storage of the execution instruction information. The guest execution control method and computer process performs the comparing and informing operations for the virtual machine system.

    摘要翻译: 一种用于具有用于保存客体虚拟机的状态描述符的主存储器的虚拟机系统的客户执行控制系统方法和计算机处理,以及多个指令处理器,每个指令处理器通过执行执行开始指令来执行客体虚拟机 客户虚拟机。 虚拟机的状态在客体虚拟机的执行期间满足预定条件时,改变状态描述符中指示客体虚拟机的执行是否要完成的执行指令信息。 执行指令信息保存在主存储器中的地址处。 访客执行控制系统包括:电路,其将正在更改的信息的主存储器中的地址与执行指令信息的主存储器中的地址进行比较,并且通知正在执行的客体虚拟机,执行指令信息已经被改变,当 正在更改的信息的主存储器中的地址与执行指令信息的主存储器中的地址相同。 访客执行控制方法和计算机进程执行虚拟机系统的比较和通知操作。

    Method of and apparatus for selecting an origin address for use in
translating a logical address in one of a plurality of virtual address
spaces to a real address in a real address space
    7.
    发明授权
    Method of and apparatus for selecting an origin address for use in translating a logical address in one of a plurality of virtual address spaces to a real address in a real address space 失效
    用于选择用于将多个虚拟地址空间中的一个虚拟地址空间中的逻辑地址转换为实际地址空间中的实际地址的源地址的方法和装置

    公开(公告)号:US5355461A

    公开(公告)日:1994-10-11

    申请号:US587031

    申请日:1990-09-24

    IPC分类号: G06F12/10

    CPC分类号: G06F12/109

    摘要: A data processing system capable of accessing multiple virtual address spaces wherein a an access register translation is performed when obtaining an origin address (STO) of a translation table to be used for address translation of a logical address into a real address. If an access register designated by an instruction has a value equal to a predetermined value, another STO stored in a control register is used instead of the STO obtained by the access register translation. Registers are provided for storing results of detection as to whether or not each of the access registers has a value equal to the predetermined value and a sector is provided selecting either the STO in the control register or the STO obtained by the access register translation based on the stored results of detection, thus eliminating a process to discriminate the values of the access registers at each access to the virtual address spaces.

    摘要翻译: 一种能够访问多个虚拟地址空间的数据处理系统,其中当获得要用于将逻辑地址转换为实际地址的地址转换的转换表的原始地址(STO)时执行访问寄存器转换。 如果由指令指定的访问寄存器具有等于预定值的值,则使用存储在控制寄存器中的另一个STO而不是通过访问寄存器转换获得的STO。 提供寄存器,用于存储每个访问寄存器是否具有等于预定值的值的检测结果,并且提供选择控制寄存器中的STO或通过访问寄存器翻译获得的STO的扇区 存储的检测结果,从而消除了在对虚拟地址空间的每次访问时区分访问寄存器的值的处理。