公开(公告)号：US08501141B2

公开(公告)日：2013-08-06

申请号：US12662006

申请日：2010-03-26

申请人： Takayuki Sato ,  Seiji Nagai ,  Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka

发明人： Takayuki Sato ,  Seiji Nagai ,  Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka

IPC分类号： C01B21/06 ,  C30B15/00 ,  C30B9/00 ,  C30B19/00 ,  C30B11/00 ,  C30B25/00 ,  C30B28/14 ,  H01L21/00 ,  H01L33/00 ,  H01L21/02 ,  H01B1/02 ,  H01B1/04

CPC分类号： C30B9/12 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02625

摘要： An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.

摘要翻译： 本发明的目的是通过Na通量法有效地添加Ge生产GaN。 在坩埚中，放置晶种衬底，使得衬底的一端保留在支撑基底上，由此籽晶衬底相对于坩埚的底表面保持倾斜，并且将镓固体和锗固体放置在 晶种基板与坩埚底面之间的空间。 然后，将钠固体置于晶种衬底上。 通过使用这种布置，当GaN晶体通过Na通量法在籽晶衬底上生长时，锗在形成钠 - 锗合金之前溶解在熔融镓中。 因此，GaN晶体可以有效地掺杂Ge。

公开(公告)号：US08216365B2

公开(公告)日：2012-07-10

申请号：US12073178

申请日：2008-02-29

申请人： Seiji Nagai ,  Shiro Yamazaki ,  Takayuki Sato ,  Katsuhiro Imai ,  Makoto Iwai ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

发明人： Seiji Nagai ,  Shiro Yamazaki ,  Takayuki Sato ,  Katsuhiro Imai ,  Makoto Iwai ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

IPC分类号： C30B25/18

CPC分类号： C30B29/403 ,  C30B9/00 ,  C30B9/10

摘要： Objects of the invention are to further enhance crystallinity and crystallinity uniformity of a semiconductor crystal produced through the flux method, and to effectively enhance the production yield of the semiconductor crystal. The c-axis of a seed crystal including a GaN single-crystal layer is aligned in a horizontal direction (y-axis direction), one a-axis of the seed crystal is aligned in the vertical direction, and one m-axis is aligned in the x-axis direction. Thus, three contact points at which a supporting tool contacts the seed crystal are present on m-plane. The supporting tool has two supporting members, which extend in the vertical direction. One supporting member has an end part, which is inclined at 30° with respect to the horizontal plane α. The reasons for supporting a seed crystal at m-plane thereof are that m-plane exhibits a crystal growth rate, which is lower than that of a-plane, and that desired crystal growth on c-plane is not inhibited. Actually, a plurality of seed crystals and supporting tools are periodically placed along the y-axis direction.

摘要翻译： 本发明的目的是进一步提高通过助焊剂法生产的半导体晶体的结晶度和结晶度均匀性，并有效提高半导体晶体的制造成品率。 包括GaN单晶层的晶种的c轴在水平方向（y轴方向）上排列，晶种的一个a轴在垂直方向上排列，并且一个m轴对齐 在x轴方向。 因此，在m平面上存在支撑工具与晶种接触的三个接触点。 支撑工具具有在垂直方向上延伸的两个支撑构件。 一个支撑构件具有相对于水平面α倾斜30°的端部。 在m面支撑晶种的原因在于，m面的晶体生长速度低于a面的晶体生长速度，c面上的期望的晶体生长没有被抑制。 实际上，沿着y轴方向周期性地放置多个晶种和支撑工具。

公开(公告)号：US07708833B2

公开(公告)日：2010-05-04

申请号：US12073904

申请日：2008-03-11

申请人： Shiro Yamazaki ,  Koji Hirata ,  Takayuki Sato ,  Seiji Nagai ,  Katsuhiro Imai ,  Makoto Iwai ,  Shuhei Higashihara ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

发明人： Shiro Yamazaki ,  Koji Hirata ,  Takayuki Sato ,  Seiji Nagai ,  Katsuhiro Imai ,  Makoto Iwai ,  Shuhei Higashihara ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

IPC分类号： C30B35/00

CPC分类号： C30B29/403 ,  C30B9/00 ,  C30B9/06 ,  Y10S117/90 ,  Y10T117/10 ,  Y10T117/1024

摘要： An object of the invention is to carry out the flux method with improved work efficiency while maintaining the purity of flux at high level and saving flux material cost. The sodium-purifying apparatus includes a sodium-holding-and-management apparatus for maintaining purified sodium (Na) in a liquid state. Liquid sodium is supplied into a sodium-holding-and-management apparatus through a liquid-sodium supply piping maintained at 100° C. to 200° C. The sodium-holding-and-management apparatus further has an argon-gas-purifying apparatus for controlling the condition of argon (Ar) gas that fills the internal space thereof. Thus, by opening and closing a faucet at desired timing, purified liquid sodium (Na) supplied from the sodium-purifying apparatus can be introduced into a crucible as appropriate via the liquid-sodium supply piping, the sodium-holding-and-management apparatus, and the piping.

摘要翻译： 本发明的目的是在保持高水平的助焊剂纯度的同时，实现提高工作效率的助焊剂方法，节约焊剂材料成本。 钠纯化装置包括用于保持液态的纯化钠（Na）的钠保持和管理装置。 液态钠通过保持在100℃至200℃的液态钠供应管道供应到保钠管理装置中。钠保持和管理装置还具有氩气净化装置 用于控制填充其内部空间的氩（Ar）气体的状态。 因此，通过在期望的时间打开和关闭水龙头，可以通过液体钠供应管道，钠保持管理装置适当地将从钠纯化装置供应的纯化液体钠（Na） ，和管道。

公开(公告)号：US07491984B2

公开(公告)日：2009-02-17

申请号：US10978438

申请日：2004-11-02

申请人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu ,  Seiji Nagai

发明人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu ,  Seiji Nagai

IPC分类号： H01L21/00

CPC分类号： H01L33/007 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02647

摘要： The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations.A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.

摘要翻译： 本发明提供了具有抑制的穿透位错产生的III族氮化物化合物半导体。 对GaN层31进行蚀刻，以形成具有例如点状，条状或格栅形状的岛状结构，由此提供沟槽/台面结构，并且在底部形成掩模4 使得掩模4的上表面位于GaN层31的顶表面之下。GaN层32被侧壁外延生长，台面的顶表面31a和用作核的沟槽的侧壁31b ，从而埋入沟槽，然后在垂直方向进行外延生长。 在通过横向外延生长形成在掩模4上方的GaN层32的上部区域中，可以防止包含在GaN层31中的穿透位错的传播。

公开(公告)号：US07163876B2

公开(公告)日：2007-01-16

申请号：US10473075

申请日：2002-03-12

申请人： Seiji Nagai ,  Masayoshi Koike ,  Kazuyoshi Tomita

发明人： Seiji Nagai ,  Masayoshi Koike ,  Kazuyoshi Tomita

IPC分类号： H01L21/36

CPC分类号： H01L21/02647 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L33/007

摘要： In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.

摘要翻译： 在其中每个生长区域D由栅格图案形成的掩模2划分的外延生长过程中，因为在相邻的每个相邻的掩模2的每个带的中心部分中形成III族氮化物化合物半导体的消耗区域C 生长区域D，组III或组V原料的边缘部分不会不必要地被供给到生长区域D的边缘部分。结果，III族或V族稀有材料供应量与边缘部分和中心 器件形成区域D的部分被抑制，器件区域的边缘部分可能不是凸的。

公开(公告)号：US07052979B2

公开(公告)日：2006-05-30

申请号：US10467566

申请日：2002-02-12

申请人： Seiji Nagai ,  Kazuyoshi Tomita ,  Shiro Yamazaki ,  Yuta Tezen ,  Toshio Hiramatsu

发明人： Seiji Nagai ,  Kazuyoshi Tomita ,  Shiro Yamazaki ,  Yuta Tezen ,  Toshio Hiramatsu

IPC分类号： H01L21/20

CPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/0066 ,  H01L33/007

摘要： When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily. The larger the cavities are formed, the more stress tends to concentrate to the projection parts, to thereby enable to separate the base substrate and the substrate layer more securely.

摘要翻译： 当在包括大量投影部分的基底基板上生长由III族氮化物化合物制成的衬底层（期望的半导体晶体）时，可以在每个突出部分之间形成其中不沉积半导体晶体的空腔，尽管它取决于 条件如每个投影部分的尺寸，每个投影部分之间的间隔和晶体生长。 因此，当基板层的厚度与突出部分的高度相比足够大时，内应力或外应力变得更容易集中于投影部分。 结果，这种应力特别地作用于朝向投影部分的剪切应力。 当剪切应力变大时，突出部分破裂。 因此，利用剪切应力使得能够容易地分离基底和基底层。 形成空穴越大，应力越倾向于集中到突出部分，从而能够更牢固地分离基底基底和基底层。

公开(公告)号：US07011707B2

公开(公告)日：2006-03-14

申请号：US10473074

申请日：2002-03-27

申请人： Seiji Nagai ,  Kazuyoshi Tomita ,  Yoshihiro Irokawa ,  Kenji Ito

发明人： Seiji Nagai ,  Kazuyoshi Tomita ,  Yoshihiro Irokawa ,  Kenji Ito

IPC分类号： C30B25/22

CPC分类号： C23C16/0272 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02664 ,  H01L33/007 ,  H01L33/32

摘要： A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.

摘要翻译： 形成反应防止层，以防止Si与形成反应防止层之后沉积的氮化镓基半导体（半导体晶体A）发生反应。 通过在牺牲层上形成包含熔点或热稳定性高于氮化镓基半导体（例如AlN）的材料的反应防止层，在沉积在反应预防的半导体衬底中不形成反应部分 通过长时间的晶体生长生长氮化镓族半导体时的层。 简而言之，由于防反射层防止硅（Si）扩散，反应部分仅在牺牲层中产生，并且即使通过生长半导体晶体也不会形成在反应防止层的上部 A在高温下长时间。

公开(公告)号：US06716655B2

公开(公告)日：2004-04-06

申请号：US10160288

申请日：2002-06-04

申请人： Seiji Nagai ,  Masayoshi Koike ,  Kazuyoshi Tomita

发明人： Seiji Nagai ,  Masayoshi Koike ,  Kazuyoshi Tomita

IPC分类号： H01L3304

CPC分类号： C30B23/02 ,  C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L33/007

摘要： An object of the invention is to produce, at high efficiency, semiconductor elements which are formed of a high-quality crystalline semiconductor having no cracks and a low dislocation density and which have excellent characteristics. Specifically, a mask formed from SiO2 film is provided on the Si(111) plane of an n-type silicon substrate, and a window portion (crystal growth region) in the shape of an equilateral triangle having a side of approximately 300 &mgr;m is formed through the mask. The three sides of the equilateral triangle are composed of three edges; each edge defined by the (111) plane and another crystal plane that is cleavable. Subsequently, a multi-layer structure of semiconductor crystals in an LED is formed through crystal growth of a Group III nitride compound semiconductor. Thus, limiting the area of one crystal growth region to a considerably small area weakens a stress applied to a semiconductor layer, thereby readily producing semiconductor elements having excellent crystallinity. In addition, semiconductor elements can be arranged in a semiconductor wafer at high packing density without loss, and each side of these semiconductor elements can be readily arranged in a line on a semiconductor wafer, thereby enhancing quality, yield, productivity, etc. of semiconductor elements.

摘要翻译： 本发明的目的是高效率地制造由没有裂纹和位错密度低且具有优异特性的高品质结晶半导体形成的半导体元件。 具体地，在n型硅衬底的Si（111）面上设置由SiO 2膜形成的掩模，并且形成具有约300μm侧面的等边三角形形状的窗口部分（晶体生长区域） 通过面具。 等边三角形的三面由三边组成， 每个边缘由（111）面和另一个可切割的晶体平面限定。 随后，通过III族氮化物化合物半导体的晶体生长，形成LED中的半导体晶体的多层结构。 因此，将一个晶体生长区域的面积限制在相当小的面积上，削弱施加到半导体层的应力，从而容易地制造具有优异结晶度的半导体元件。 此外，半导体元件可以以高封装密度无损耗地布置在半导体晶片中，并且这些半导体元件的每一侧可以容易地布置在半导体晶片上的线上，从而提高半导体的质量，产量，生产率等 元素。

公开(公告)号：US06471770B2

公开(公告)日：2002-10-29

申请号：US09748234

申请日：2000-12-27

申请人： Masayoshi Koike ,  Seiji Nagai

发明人： Masayoshi Koike ,  Seiji Nagai

IPC分类号： C30B2522

CPC分类号： H01L21/0254 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02472 ,  H01L21/02491 ,  H01L21/02505 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/0079 ,  H01S5/0202 ,  H01S5/0213 ,  H01S5/32341

摘要： A thick GaN layer is grown on sapphire through an Au layer at a temperature lower than the melting point of 1064° C. of the Au layer, and temperature of a sample is raised to reach and exceed the melting point of the Au layer so that the Au layer is dissolved. In this state, the sapphire and GaN layer are separated from each other.

摘要翻译： 在低于Au层的1064℃的熔点的温度下，通过Au层在蓝宝石上生长厚的GaN层，使样品的温度升高到超过Au层的熔点，使得 Au层溶解。 在这种状态下，蓝宝石和GaN层彼此分离。

公开(公告)号：US06326236B1

公开(公告)日：2001-12-04

申请号：US09497814

申请日：2000-02-03

申请人： Norikatsu Koide ,  Shinya Asami ,  Junichi Umezaki ,  Masayoshi Koike ,  Shiro Yamasaki ,  Seiji Nagai

发明人： Norikatsu Koide ,  Shinya Asami ,  Junichi Umezaki ,  Masayoshi Koike ,  Shiro Yamasaki ,  Seiji Nagai

IPC分类号： H01L2144

CPC分类号： H01L33/32 ,  B82Y20/00 ,  H01L29/155 ,  H01L33/06 ,  Y10S438/933

摘要： In a method of manufacturing a semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of InY1Ga1−Y1N (Y1≧0) and a quantum well layer being made of InY2Ga1−Y2N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.