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公开(公告)号：US4783783A
公开(公告)日：1988-11-08
申请号：US888936
申请日：1986-07-24
申请人： Seiji Nagai , Takaaki Nishiyama , Hiromichi Kainoh , Fujio Wakui
发明人： Seiji Nagai , Takaaki Nishiyama , Hiromichi Kainoh , Fujio Wakui
CPC分类号： G06F9/3865 , G06F11/10 , G06F11/076 , G06F11/14
摘要： A data processing system includes a multistage pipeline arithmetic/logic operation unit for implementing an arithmetic or logic operation for sets of element data sequentially and storing operational results sequentially in a memory using a single instruction. Check information indicative of the presence or absence of a fault occurring in each stage of the pipeline operation unit is moved in synchronism with the advancement of stages of the pipeline operation unit. A request control unit for storing the operational result in the memory suppresses the storing of the operational result in the memory if check information indicates a fault of the operational result which is being stored in the memory. The request control unit issues storage requests, which are counted by a counter. The counter indicates the number of elements stored normally in the memory.
摘要翻译： 一种数据处理系统包括：多级流水线运算/逻辑运算单元，用于依次执行元件数据集的运算或逻辑运算，并使用单个指令将运算结果顺序存储在存储器中。 与流水线操作单元的各级的前进同步地移动表示流水线操作单元的各个阶段中出现故障的存在或不存在的信息。 如果检查信息指示存储在存储器中的操作结果的故障，则将存储操作结果存储在存储器中的请求控制单元禁止将操作结果存储在存储器中。 请求控制单元发出由计数器计数的存储请求。 计数器指示存储器中正常存储的元素数量。
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2.发明授权Fault recovering system provided in highly reliable computer system having duplicated processors 失效在具有重复处理器的高度可靠的计算机系统中提供的故障恢复系统
公开(公告)号：US5748873A
公开(公告)日：1998-05-05
申请号：US686486
申请日：1996-07-26
申请人： Hiroshi Ohguro , Koichi Ikeda , Takaaki Nishiyama , Hiroshi Iwamoto , Kenichi Kurosawa , Tetsuaki Nakamikawa , Michio Morioka
发明人： Hiroshi Ohguro , Koichi Ikeda , Takaaki Nishiyama , Hiroshi Iwamoto , Kenichi Kurosawa , Tetsuaki Nakamikawa , Michio Morioka
CPC分类号： G06F11/165 , G06F11/1658 , G06F11/1679
摘要： A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state of the processor in amain memory and diagnosing factor of the detected mismatch. If the process is recognized to be continued in a duplex mode, the processors are re-synchronized by a processor reset, and initialize themselves and restore the internal information saved in the main memory for continuing the process having been proceeded before the fault occurred.
摘要翻译： 高度可靠的计算机系统旨在复制处理器，将处理器的输出相互比较，并提高处理器系统输出的有效性。 如果检测到输出之间的不匹配，则其中一个处理器执行将处理器的内部状态保存在大量存储器中并诊断检测到的失配的因素的处理。 如果该处理被识别为以双工模式继续，则处理器通过处理器复位重新同步，并且自己初始化并恢复保存在主存储器中的内部信息，以便继续在故障发生之前进行的处理。
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公开(公告)号：US4654785A
公开(公告)日：1987-03-31
申请号：US637137
申请日：1984-08-03
CPC分类号： G06F9/30094 , G06F9/3842
摘要： An information processing system having a plurality of arithmetic units such as a general instruction arithmetic unit and a floating point instruction arithmetic unit comprises means provided for each of the arithmetic units, for generating a condition code for use in branch judgement of a conditional branch instruction, branch judgement means provided in each arithmetic unit for judging success or failure of a branch of the conditional branch instruction by using the condition generated by the respective code generating means, and a judgement unit decision circuit responsive to the operation state of each arithmetic unit for generating an instruction signal indicating which of the judging means is to be operated to and supplying it to the branch judgement means, whereby branch control is carried out by using either one of the branch judgement results obtained in the respective arithmetic units as a valid one.
摘要翻译： 具有诸如通用指令运算单元和浮点指令运算单元的多个算术单元的信息处理系统包括为每个运算单元提供的装置，用于生成用于条件转移指令的分支判断的条件代码， 分支判断装置，设置在每个运算单元中，用于通过使用由各个代码生成装置生成的条件来判断条件转移指令的分支的成败;以及判断单元判定电路，其响应于每个运算单元的运行状态来生成 指示哪个判断装置被操作并将其提供给分支判断装置的指令信号，由此通过使用在各个运算单元中获得的分支判断结果中的任一个作为有效的执行来执行分支控制。
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