公开(公告)号：US11049470B2

公开(公告)日：2021-06-29

申请号：US16808449

申请日：2020-03-04

Applicant: FUJITSU LIMITED

Inventor： Kohji Yamada

IPC: G09G5/00 ,  H04L29/06

Abstract: An apparatus receives pieces of image data of respective frames from a server apparatus, where each of the pieces of image data represents a display screen reflecting a result of processing corresponding to an input operation performed on the apparatus. The apparatus, in response to reception of a piece of image data of a first frame among the frames from the server apparatus, controls a display timing of the first frame, based on an occurrence state of an input operation on the apparatus.

公开(公告)号：US11516503B2

公开(公告)日：2022-11-29

申请号：US17172116

申请日：2021-02-10

Applicant: FUJITSU LIMITED

Inventor： Kohji Yamada

IPC: H04N19/577 ,  H04N19/543 ,  H04N19/423

Abstract: An encoding apparatus, includes a memory; and a processor coupled to the memory and configured to: perform intra-screen prediction encoding on an image of a region of a still image cut out from a first decoded image corresponding to a screen image before a predetermined region is switched from a video to a still image, generate a second decoded image obtained by decoding information for which the intra-screen prediction is performed, and when a first screen image after the predetermined region is switched from a video to a still image is received, perform inter-screen prediction encoding on an image of a region of a still image cut out from the first screen image after switching to a still image, by referring to the generated second decoded image.

公开(公告)号：US11218705B2

公开(公告)日：2022-01-04

申请号：US16937689

申请日：2020-07-24

Applicant: FUJITSU LIMITED

Inventor： Guillaume Denis Christian Barroux ,  Kohji Yamada ,  Akira Nakagawa ,  Kimihiko Kazui

IPC: H04N19/159 ,  H04N19/13 ,  H04N19/176 ,  H04N19/46

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: determine an angle of intra prediction for a block to be encoded in an image included in a video, and encode the block to be encoded using the angle of intra prediction; generate a bit value indicating an estimation result of the angle using a locally decoded pixel value of an encoded pixel adjacent to the block to be encoded; generate a bit string indicating the angle of intra prediction and generate flag information indicating whether a partial bit value of the bit string matches the bit value indicating an estimation result of the angle; and encode the flag information by a first encoding method and encode a remaining bit value of the bit string by a second encoding method.

公开(公告)号：US10897622B2

公开(公告)日：2021-01-19

申请号：US16540116

申请日：2019-08-14

Applicant: FUJITSU LIMITED

Inventor： Kohji Yamada

IPC: H04N19/172 ,  H04N19/196

Abstract: An encoding device includes a memory, and a processor coupled to the memory and the processor configured to extract a first line-drawing region from a first image in a plurality of images, by replacing the first line-drawing region of the first image with an image which is included in a second image preceding the first image in the plurality of images and corresponds to the first line-drawing region, generate a third image, generate video encoding information by performing a video encoding processing based on the third image, generate line-drawing encoding information by performing a line-drawing encoding processing based on the first line-drawing region, and transmit the video encoding information and the line-drawing encoding information to a decoding device.

公开(公告)号：US20130156257A1

公开(公告)日：2013-06-20

申请号：US13659986

申请日：2012-10-25

Applicant: Fujitsu Limited

Inventor： Taizo ANAN ,  Kohji Yamada

IPC: G06K9/00

CPC classification number: H04N1/32101 ,  H04L9/3247 ,  H04N1/32277 ,  H04N2201/3235 ,  H04N2201/3236 ,  H04N2201/3281 ,  H04N2201/3283

Abstract: An image processing device includes a frequency calculation part configured to calculate frequency coefficients of an image, a coefficient selection part configured to select plural pairs of the frequency coefficients from the calculated frequency coefficients, a code generation part configured to generate a code based on a comparison result between an absolute value of a difference between the two frequency coefficients of each of the selected pairs and a threshold, and a magnitude relationship between the two frequency coefficients, and a signature generation part configured to encrypt the generated code with a private key to generate a digital signature.

Abstract translation: 图像处理装置包括频率计算部，其被配置为计算图像的频率系数;系数选择部，被配置为从所计算的频率系数中选择多对频率系数;代码生成部，被配置为基于比较生成代码 在所选择的对中的每一个的两个频率系数和阈值之间的差的绝对值之间以及两个频率系数之间的幅度关系之间产生的结果，以及被配置为用私钥对生成的代码进行加密的签名生成部， 数字签名。

公开(公告)号：US11557018B2

公开(公告)日：2023-01-17

申请号：US17380889

申请日：2021-07-20

Applicant: FUJITSU LIMITED

Inventor： Kohji Yamada

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/14 ,  G06F9/50

Abstract: An image processing apparatus of transferring a display image to a client machine, the display image being an image to be displayed on a display device associated with the client machine, the image processing apparatus including: a memory; and a processor coupled to the memory, the processor being configured to perform processing, the processing including: executing a first transfer process configured to transfer only moving image data as the display image; executing a second transfer process configured to transfer moving image data and still image data as the display image; and executing a control process configured to select either the executing of the first transfer process or the executing of the second transfer process, by using a frame rate of the display image and a state of a graphics processing unit (GPU) circuitry configured to perform a process related to an image.

公开(公告)号：US10250891B2

公开(公告)日：2019-04-02

申请号：US15068847

申请日：2016-03-14

Applicant: FUJITSU LIMITED

Inventor： Kimihiko Kazui ,  Kohji Yamada

IPC: H04N19/142 ,  H04N19/107 ,  H04N19/105 ,  H04N19/136 ,  H04N19/503 ,  H04N19/51 ,  H04N19/179 ,  H04N19/172 ,  H04N19/70 ,  H04N19/58 ,  H04N19/186 ,  H04N19/40

Abstract: A storage circuit stores a decoded image of a coded image that is coded before a coding target image included in a video to which the still-image coding and the video coding are applied. A video coding circuit codes the coding target image by inter prediction coding that uses the decoded image as a reference image when the still-image coding is applied to the mage that is one image previous to the coding target image and the video coding is applied to the coding target image.