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公开(公告)号:US07353347B2
公开(公告)日:2008-04-01
申请号:US10947877
申请日:2004-09-23
申请人: Fuk Ho Pius Ng , Y. Paul Chiang
发明人: Fuk Ho Pius Ng , Y. Paul Chiang
CPC分类号: G11C15/00
摘要: A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.
摘要翻译: 提供可重构状态机。 状态机包括用于存储当前状态的当前状态寄存器和每个状态机状态的至少一个可编程状态条目。 每个可编程项目包括多个外部信号输入,当前状态标签,至少一个下一个状态条件和相应的下一个状态输出。 下一状态匹配电路将当前状态与当前状态标签进行比较,并将下一状态条件中的每一个与至少一个外部信号输入进行比较,以产生下一状态匹配输出。
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公开(公告)号:US06369855B1
公开(公告)日:2002-04-09
申请号:US08962514
申请日:1997-10-31
申请人: Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人: Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号: H04N726
CPC分类号: H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要: An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
摘要翻译: 提供了一种改进的视听电路,其包括用于接收传输数据分组流的传输分组解析电路,用于初始化所述集成电路并用于处理所述数据分组流的部分的CPU电路,用于存储数据的ROM电路,RAM 用于存储数据的电路,用于解码所述数据分组流的音频部分的音频解码器电路,用于解码所述数据分组流的视频部分的视频解码器电路,用于对所述数据分组流的视频部分进行编码的NTSC / PAL编码电路, OSD协处理器电路,用于处理所述数据分组的OSD部分,业务控制器电路,在所述集成电路的部分之间移动所述数据分组流的部分,扩展总线接口电路,P1394接口电路,通信协处理器电路,连接的地址总线 连接到所述电路,以及连接到所述电路的数据总线。
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公开(公告)号:US06310657B1
公开(公告)日:2001-10-30
申请号:US09679000
申请日:2000-10-04
申请人: Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人: Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号: H04N550
CPC分类号: H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要: An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要翻译: 其中CPU在工作存储器空间中生成窗口的屏幕显示系统还提供对工作存储器空间中的窗口地址的实时计算。 这可以消除对单独的帧缓冲存储器的需要。
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