摘要:
An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要:
An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
摘要:
A transport stream parser system is provided that utilizes an intermediate buffer for containing packets after processing with an associated flag and then use a processor for further processing of packets selected by such flags.
摘要:
An on-screen display with variable resolution capability permits respective parts of a screen to be processed according to their respective resolution requirements. For any active window in the on-screen display, the data format used in memory to represent the pixels of that window can be determined, thereby permitting the window resolution to vary from window to window.
摘要:
A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.
摘要:
In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要:
A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic may comprise the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction's operation (e.g., the inclusion of read or write barrier operations to support a garbage collector).
摘要:
A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要:
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer. The L2 cache, along with all of the TLBs and &mgr;TLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task. Configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.
摘要:
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. Multiple detection circuitry responds to several cache access requests concurrently. Multiple ports in the cache service multiple requesters concurrently if concurrent hits are determined by the detection circuitry.