-
公开(公告)号：US11360895B2
公开(公告)日：2022-06-14
申请号：US16791957
申请日：2020-02-14
申请人： Fungible, Inc.
IPC分类号： G06F12/0815 , G06F12/0804 , G06F15/173
摘要： Methods and apparatus for memory management are described. In one example, this disclosure describes a method that includes executing, by a first processing unit, first work unit operations specified by a first work unit message, wherein execution of the first work unit operations includes accessing data from shared memory included within the computing system, modifying the data, and storing the modified data in a first cache associated with the first processing unit; identifying, by the computing system, a second work unit message that specifies second work unit operations that access the shared memory; updating, by the computing system, the shared memory by storing the modified data in the shared memory; receiving, by the computing system, an indication that updating the shared memory with the modified data is complete; and enabling the second processing unit to execute the second work unit operations.
-
公开(公告)号：US11303472B2
公开(公告)日：2022-04-12
申请号：US16031921
申请日：2018-07-10
申请人： Fungible, Inc.
发明人： Pradeep Sindhu , Jean-Marc Frailong , Bertrand Serlet , Wael Noureddine , Felix A. Marti , Deepak Goel , Rajan Goyal
IPC分类号： G06F13/12 , H04L12/46 , G06F13/16 , G06F13/42 , G06F12/0817 , H04L49/253 , H04L49/10 , H04L12/54 , H04L45/02 , G06F12/0811 , H04L12/70
摘要： A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.
-
公开(公告)号：US11258796B2
公开(公告)日：2022-02-22
申请号：US16504112
申请日：2019-07-05
申请人： Fungible, Inc.
摘要： A key-value store supporting GET, PUT and DELETE operations, serializes multiple clients using two locks, and that supports asynchronous resizing. The locking scheme includes an operation of holding two locks, one for the key involved in the operation, one for the page currently searched or updated. The store can either be a single volume holding keys and data or can be organized as a directory volume referencing a number of data volumes organized by data-size ranges. The scheme also supports asynchronous resizing of the directory while continuing to perform operations.
-
公开(公告)号：US20200183841A1
公开(公告)日：2020-06-11
申请号：US16791957
申请日：2020-02-14
申请人： Fungible, Inc.
IPC分类号： G06F12/0815 , G06F15/173 , G06F12/0804
摘要： Methods and apparatus for memory management are described. In one example, this disclosure describes a method that includes executing, by a first processing unit, first work unit operations specified by a first work unit message, wherein execution of the first work unit operations includes accessing data from shared memory included within the computing system, modifying the data, and storing the modified data in a first cache associated with the first processing unit; identifying, by the computing system, a second work unit message that specifies second work unit operations that access the shared memory; updating, by the computing system, the shared memory by storing the modified data in the shared memory; receiving, by the computing system, an indication that updating the shared memory with the modified data is complete; and enabling the second processing unit to execute the second work unit operations.
-
公开(公告)号：US10303375B2
公开(公告)日：2019-05-28
申请号：US15269457
申请日：2016-09-19
申请人： Fungible Inc.
发明人： Deepak Goel , Pradeep Sindhu , Bertrand Serlet , Wael Noureddine , Paul Kim
摘要： Methods and apparatus for buffer allocation and memory management are described. A plurality of buffers of a memory may be allocated, by a memory controller, with the buffers having variable sizes. The memory controller may maintain a mapping table that associates each of a plurality of access keys to a respective one of a plurality of page addresses of a plurality of pages of the memory. Each of the buffers may respectively include one or more contiguous pages of the plurality of pages of the memory. Each page of the plurality of pages may include one or more blocks of the memory.
-
公开(公告)号：US20190013965A1
公开(公告)日：2019-01-10
申请号：US16031676
申请日：2018-07-10
申请人： Fungible, Inc.
发明人： Pradeep Sindhu , Jean-Marc Frailong , Bertrand Serlet , Wael Noureddine , Felix A. Marti , Deepak Goel , Paul Kim , Rajan Goyal , Aibing Zhou
IPC分类号： H04L12/46 , H04L12/54 , H04L12/751
摘要： A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center.
-
公开(公告)号：US10725825B2
公开(公告)日：2020-07-28
申请号：US16031945
申请日：2018-07-10
申请人： Fungible, Inc.
发明人： Pradeep Sindhu , Jean-Marc Frailong , Wael Noureddine , Felix A. Marti , Deepak Goel , Rajan Goyal , Bertrand Serlet
IPC分类号： G06F9/46 , G06F9/50 , G06F15/173
摘要： A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.
-
公开(公告)号：US10565112B2
公开(公告)日：2020-02-18
申请号：US15949892
申请日：2018-04-10
申请人： Fungible, Inc.
IPC分类号： G06F12/0815 , G06F12/0804 , G06F15/173
摘要： Methods and apparatus for memory management are described. In a disclosed embodiment, a system has a first and a second processor, with each processor able to access a memory system. A first work unit is received for execution by the first processor, with the memory system being accessed. A second work unit is generated for execution by a second processor upon execution of a first work unit. Only after the memory system is updated does processing of the second work unit by the second processor occur. This work unit message based ordering provides relay consistency for memory operations of multiple processors.
-
公开(公告)号：US20190012278A1
公开(公告)日：2019-01-10
申请号：US16031921
申请日：2018-07-10
申请人： Fungible, Inc.
发明人： Pradeep Sindhu , Jean-Marc Frailong , Bertrand Serlet , Wael Noureddine , Felix A. Marti , Deepak Goel , Rajan Goyal
摘要： A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.
-
公开(公告)号：US20180081580A1
公开(公告)日：2018-03-22
申请号：US15269457
申请日：2016-09-19
申请人： Fungible Inc.
发明人： Deepak Goel , Pradeep Sindhu , Bertrand Serlet , Wael Noureddine , Paul Kim
IPC分类号： G06F3/06 , G06F12/1009
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F12/0292 , G06F2212/1008 , G06F2212/1044
摘要： Methods and apparatus for buffer allocation and memory management are described. A plurality of buffers of a memory may be allocated, by a memory controller, with the buffers having variable sizes. The memory controller may maintain a mapping table that associates each of a plurality of access keys to a respective one of a plurality of page addresses of a plurality of pages of the memory. Each of the buffers may respectively include one or more contiguous pages of the plurality of pages of the memory. Each page of the plurality of pages may include one or more blocks of the memory.
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.016 秒)