公开(公告)号：US09837555B2

公开(公告)日：2017-12-05

申请号：US14687549

申请日：2015-04-15

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/68 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L29/1095 ,  H01L29/66189 ,  H01L29/94

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US20160308073A1

公开(公告)日：2016-10-20

申请号：US14687549

申请日：2015-04-15

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/10

CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L29/1095 ,  H01L29/66189 ,  H01L29/94

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

Abstract translation: 本文提供了用于低损耗耦合电容器结构的实施例。 这些实施例包括n型变容二极管（NVAR）配置和p型变容二极管（PVAR）配置。 NVAR配置中的结构包括Pub掺杂半导体衬底（Psub），Psub中的深n掺杂半导体阱（DNW）和DNW中的p掺杂半导体阱（P阱）。 电路结构还包括P阱内的p掺杂半导体材料的源极端子和P阱内的p掺杂半导体材料的漏极端子。 另外，电路结构包括在P阱的表面上的绝缘栅极，包括多层金属线的金属图案，以及穿过金属线的多个通孔。 通孔是将金属线连接到栅极，源极端子和漏极端子的触点。

公开(公告)号：US20200321479A1

公开(公告)日：2020-10-08

申请号：US16813702

申请日：2020-03-09

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence E. Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/94 ,  H01L27/08 ,  H01L29/10

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US10586878B2

公开(公告)日：2020-03-10

申请号：US15830927

申请日：2017-12-04

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/94 ,  H01L29/66 ,  H01L29/10 ,  H01L27/08

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US20180090627A1

公开(公告)日：2018-03-29

申请号：US15830927

申请日：2017-12-04

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/94 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L29/1095 ,  H01L29/66189 ,  H01L29/94

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US11569393B2

公开(公告)日：2023-01-31

申请号：US16813702

申请日：2020-03-09

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence E. Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L27/08 ,  H01L29/10 ,  H01L29/94 ,  H01L29/93 ,  H01L29/66

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US10715195B2

公开(公告)日：2020-07-14

申请号：US16007711

申请日：2018-06-13

Applicant: Futurewei Technologies, Inc.

Inventor： Matthew Richard Miller ,  Brian Creed ,  Terrie McCain

IPC: H04B1/16 ,  H03D7/12 ,  H03F3/45

Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.

公开(公告)号：US20190386694A1

公开(公告)日：2019-12-19

申请号：US16007711

申请日：2018-06-13

Applicant: Futurewei Technologies, Inc.

Inventor： Matthew Richard Miller ,  Brian Creed ,  Terrie McCain

IPC: H04B1/16 ,  H03F3/45 ,  H03D7/12

Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.