中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.018 seconds)

    Apparatus and method for a low loss coupling capacitor
    1.
    发明授权
    Apparatus and method for a low loss coupling capacitor 有权

    公开(公告)号：US11569393B2

    公开(公告)日：2023-01-31

    申请号：US16813702

    申请日：2020-03-09

    Applicant: Futurewei Technologies, Inc.

    Inventor： Brian Creed ,  Lawrence E. Connell ,  Kent Jaeger ,  Matthew Richard Miller

    IPC: H01L27/08 ,  H01L29/10 ,  H01L29/94 ,  H01L29/93 ,  H01L29/66

    Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

    High Isolation Switch
    2.
    发明申请
    High Isolation Switch 审中-公开
    高隔离开关

    公开(公告)号：US20160372464A1

    公开(公告)日：2016-12-22

    申请号：US15256154

    申请日：2016-09-02

    Applicant: Futurewei Technologies, Inc.

    Inventor： Kent Jaeger ,  Lawrence Connell

    IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06

    CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L23/522 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/78

    Abstract: An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.

    Abstract translation: 实施例集成电路包括开关和开关上的导线。 开关包括栅极，半导体衬底的顶表面处的第一源极/漏极区域和半导体衬底的顶表面处的第二源极/漏极区域。 第一源极/漏极区域和第二源极/漏极区域设置在栅极的相对侧上。 第一导电线的至少一部分与栅极对准，并且第一导电线电耦合到地。

    Low Power High Speed Quadrature Generator
    3.
    发明申请
    Low Power High Speed Quadrature Generator 有权
    低功率高速正交发生器

    公开(公告)号：US20140361821A1

    公开(公告)日：2014-12-11

    申请号：US13934306

    申请日：2013-07-03

    Applicant: Futurewei Technologies, Inc.

    Inventor： Lawrence E. Connell ,  Daniel P. McCarthy ,  Brian T. Creed ,  Kent Jaeger

    IPC: H03K3/012

    CPC classification number: H03K3/356104

    Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.

    Abstract translation: 一种包括锁存器的装置，包括差分反相器，其被配置为接收差分输入信号并产生差分输出信号，耦合到差分反相器的一对交叉耦合反相器，以及被配置为将差分反相器耦合到电压的第一时钟开关 源，第二时钟开关，其被配置为将所述差分逆变器耦合到地，其中所述第一时钟切换器和所述第二时钟切换器被配置为接收差分时钟信号，并且其中所述第一时钟切换器和所述第二时钟切换器都是打开的， 两个闭合取决于差分时钟信号，第二锁存器，其中第一锁存器和第二锁存器被配置为分频器，以及耦合到每个锁存器的逻辑电路，其中逻辑电路被配置为同时产生同相 参考输出信号和正交输出信号。

    Programmable driver for frequency mixer
    4.
    发明授权
    Programmable driver for frequency mixer 有权

    公开(公告)号：US10404212B1

    公开(公告)日：2019-09-03

    申请号：US16056175

    申请日：2018-08-06

    Applicant: Futurewei Technologies, Inc.

    Inventor： Lawrence E. Connell ,  Kent Jaeger

    IPC: H04B1/30 ,  H03D7/14 ,  H03D7/16 ,  H03F1/32 ,  H03F1/30

    Abstract: The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

    Apparatus and method for a low loss coupling capacitor
    5.
    发明授权
    Apparatus and method for a low loss coupling capacitor 有权

    公开(公告)号：US09837555B2

    公开(公告)日：2017-12-05

    申请号：US14687549

    申请日：2015-04-15

    Applicant: Futurewei Technologies, Inc.

    Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

    IPC: H01L29/93 ,  H01L29/10 ,  H01L29/68 ,  H01L29/66 ,  H01L29/94

    CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L29/1095 ,  H01L29/66189 ,  H01L29/94

    Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

    Device and method for a high isolation switch
    9.
    发明授权
    Device and method for a high isolation switch 有权
    高隔离开关的装置和方法

    公开(公告)号：US09449969B1

    公开(公告)日：2016-09-20

    申请号：US14730018

    申请日：2015-06-03

    Applicant: Futurewei Technologies, Inc.

    Inventor： Kent Jaeger ,  Lawrence E. Connell

    IPC: H01L29/76 ,  H01L27/088 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L23/522 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/78

    Abstract: An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.

    Abstract translation: 实施例集成电路包括开关和开关上的导线。 开关包括栅极，半导体衬底的顶表面处的第一源极/漏极区域和半导体衬底的顶表面处的第二源极/漏极区域。 第一源极/漏极区域和第二源极/漏极区域设置在栅极的相对侧上。 第一导电线的至少一部分与栅极对准，并且第一导电线电耦合到地。

    Low power high speed quadrature generator
    10.
    发明授权
    Low power high speed quadrature generator 有权
    低功率高速正交发生器

    公开(公告)号：US09166571B2

    公开(公告)日：2015-10-20

    申请号：US13934306

    申请日：2013-07-03

    Applicant: Futurewei Technologies, Inc.

    Inventor： Lawrence E. Connell ,  Daniel P. McCarthy ,  Brian T. Creed ,  Kent Jaeger

    IPC: H03K3/00 ,  H03K3/356

    CPC classification number: H03K3/356104

    Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.

    Abstract translation: 一种包括锁存器的装置，包括差分反相器，其被配置为接收差分输入信号并产生差分输出信号，耦合到差分反相器的一对交叉耦合反相器，以及被配置为将差分反相器耦合到电压的第一时钟开关 源，第二时钟开关，其被配置为将所述差分逆变器耦合到地，其中所述第一时钟切换器和所述第二时钟切换器被配置为接收差分时钟信号，并且其中所述第一时钟切换器和所述第二时钟切换器都是打开的， 两个闭合取决于差分时钟信号，第二锁存器，其中第一锁存器和第二锁存器被配置为分频器，以及耦合到每个锁存器的逻辑电路，其中逻辑电路被配置为同时产生同相 参考输出信号和正交输出信号。

Patent Agency Ranking