公开(公告)号：US07203824B2

公开(公告)日：2007-04-10

申请号：US09906381

申请日：2001-07-16

申请人： Brent Bean ,  G. Glenn Henry ,  Thomas C. McDonald

发明人： Brent Bean ,  G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F9/32

CPC分类号： G06F9/30149 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/3867

摘要： A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

公开(公告)号：US07234045B2

公开(公告)日：2007-06-19

申请号：US11208302

申请日：2005-08-19

申请人： G. Glenn Henry ,  Brent Bean ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Brent Bean ,  Thomas C. McDonald

IPC分类号： G06F9/32

CPC分类号： G06F9/3804 ,  G06F9/3806

摘要： A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

摘要翻译： 微处理器中的分支控制装置。 该装置包括分支目标地址高速缓存（BTAC），其缓存分支指令是否跨越两个高速缓存线路的指示。 当包含分支指令的第一部分的第一高速缓存线的指令高速缓冲存取器地址在BTAC中命中时，BTAC输出转移指令的目标地址并指示换行条件。 目标地址存储在寄存器中。 下一个顺序取出地址选择包含分支指令第二部分的第二个高速缓存行。 在取出包含分支指令的两条高速缓存行之后，将来自寄存器的目标地址提供给指令高速缓存，以便获取包含该分支的目标指令的第三高速缓存行。 三条缓存行按顺序存储在用于解码的指令缓冲器中。

公开(公告)号：US08671285B2

公开(公告)日：2014-03-11

申请号：US13091487

申请日：2011-04-21

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC分类号： G06F21/00

CPC分类号： H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

摘要： A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key.

摘要翻译： 提取单元（a）从微处理器的指令高速缓冲存储器获取指令数据块; （b）使用数据实体在块上执行异或以产生明文指令数据; 和（c）将明文指令数据提供给指令译码单元。 在第一种情况下，块包括加密指令数据，数据实体是解密密钥。 在第二种情况下，该块包括未加密的指令数据，并且数据实体为布尔零。 执行（a），（b）和（c）所需的时间在第一和第二实例中是相同的，而不管该块是加密还是未加密。 解密密钥生成器从多个密钥中选择第一和第二密钥，旋转第一密钥，并且基于获取地址的部分，将旋转后的第一密钥加到/从第二密钥中加减乘以产生解密密钥。

公开(公告)号：US08131984B2

公开(公告)日：2012-03-06

申请号：US12481499

申请日：2009-06-09

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC分类号： G06F9/32

CPC分类号： G06F9/30058 ,  G06F9/3867

摘要： A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.

摘要翻译： 微处理器包括控制寄存器，其存储影响微处理器的操作的控制值。 指令集架构包括基于存储在控制寄存器中的控制值来指定分支条件的条件转移指令，以及更新控制寄存器中的控制值的串行化指令。 微处理器通过串行化指令之前的指令完成对标志，寄存器和存储器的所有修改，并在串行化指令之前取出并执行下一条指令，将所有缓冲写入消耗到存储器中。 响应串行化指令，执行单元更新控制寄存器中的控制值。 取出单元基于存储在控制寄存器中的控制值来取得，解码和无条件地正确地解析和退出条件转移指令，而不是将条件转移指令分派到要解析的执行单元。

公开(公告)号：US07975132B2

公开(公告)日：2011-07-05

申请号：US12481074

申请日：2009-06-09

申请人： Brent Bean ,  Terry Parks ,  G. Glenn Henry

发明人： Brent Bean ,  Terry Parks ,  G. Glenn Henry

IPC分类号： G06F9/38

CPC分类号： G06F9/30054 ,  G06F9/3806 ,  G06F9/3844

摘要： A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.

摘要翻译： 具有多个呼叫/返回栈（CRS）的微处理器正确地解析了呼叫或返回指令，而不是向要解析的微处理器的执行单元发出指令。 微处理器获取一个调用或返回指令，并确定该指令是否是在获取尚未解决的条件分支指令之后获取的第一个调用或返回指令。 如果状态存在，则微处理器将当前CRS的内容复制到另一个CRS，并将其他CRS指定为当前CRS。 如果指令是呼叫指令，微处理器将呼叫指令之后的下一个顺序指令的地址推送到当前CRS上，并在调用指令目标地址处取指令。 如果指令是返回指令，则微处理器从当前CRS中弹出第二个返回地址，并在第二个返回地址处获取指令。

公开(公告)号：US20100205404A1

公开(公告)日：2010-08-12

申请号：US12481487

申请日：2009-06-09

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3867

摘要： A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is implemented by the non-user program. An instruction decoder decodes the user program instructions and saves a state in response to decoding the user program instruction that is implemented by the non-user program. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the non-user program other than the conditional branch instruction. A second fetch unit fetches the non-user program instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.

摘要翻译： 微处理器包括存储器，其存储非用户程序的指令以实现微处理器的用户可见指令集的用户程序指令。 非用户程序包括条件分支指令。 第一提取单元获取包括由非用户程序实现的指令的用户程序的指令。 指令解码器对用户程序指令进行解码，并且响应于解码由非用户程序实现的用户程序指令而保存状态。 执行单元执行由第一取出单元取出的用户程序指令，并执行非条件转移指令以外的非用户程序的指令。 第二取出单元从存储器取出非用户程序指令，并且基于保存的状态解析条件转移指令，而不向执行单元发送条件转移指令来解析条件转移指令。

公开(公告)号：US08700919B2

公开(公告)日：2014-04-15

申请号：US13091547

申请日：2011-04-21

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC分类号： G06F21/00

CPC分类号： H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

摘要： A fetch unit fetches a sequence of blocks of encrypted instructions of an encrypted program from an instruction cache at a corresponding sequence of fetch address values. While fetching each block of the sequence, the fetch unit generates a decryption key as a function of key values and the corresponding fetch address value, and decrypts the encrypted instructions using the generated decryption key by XORing them together. A switch key instruction instructs the microprocessor to update the key values in the fetch unit while the fetch unit is fetching the sequence of blocks. The fetch unit inherently provides an effective decryption key length that depends upon the function and amount of key values used. Including one or more switch key instructions within the encrypted program increases the effective decryption key length up to the encrypted program length.

摘要翻译： 取出单元以相应的获取地址值序列从指令高速缓存中提取加密程序的加密指令的一系列块。 在提取序列的每个块时，提取单元根据密钥值和相应的获取地址值产生解密密钥，并且通过将它们一起进行异或来解密加密的指令。 切换键指令指示微处理器在获取单元获取块序列时更新提取单元中的键值。 提取单元固有地提供了一个有效的解密密钥长度，这取决于所使用的密钥值的功能和数量。 在加密程序中包括一个或多个切换密钥指令将有效的解密密钥长度增加到加密的程序长度。

公开(公告)号：US08245017B2

公开(公告)日：2012-08-14

申请号：US12481118

申请日：2009-06-09

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/30058 ,  G06F9/3867

摘要： A microprocessor includes a first branch condition state and a second branch condition state. The microprocessor also includes a conditional branch instruction of a first type that instructs the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state until other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type have updated the first branch condition state. A conditional branch instruction of a second type instructs the microprocessor to correctly resolve the conditional branch instruction of the second type based on the second branch condition state without regard to whether other instructions within the microprocessor that update the second branch condition state and that are older than the conditional branch instruction of the second type have yet updated the second branch condition state.

摘要翻译： 微处理器包括第一分支状态和第二分支状态。 微处理器还包括第一类型的条件转移指令，指示微处理器基于第一转移条件状态等待正确地解析第一类型的条件转移指令，直到微处理器内的其他指令更新第一分支状态和 比第一类型的条件分支指令更旧的第一分支条件状态。 第二类型的条件分支指令指示微处理器基于第二分支条件状态来正确地解析第二类型的条件分支指令，而不考虑微处理器内是否更新第二分支条件状态并且比第二分支状态更新的其它指令 第二类型的条件分支指令还更新了第二分支条件状态。

公开(公告)号：US20120096282A1

公开(公告)日：2012-04-19

申请号：US13091487

申请日：2011-04-21

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC分类号： G06F21/00 ,  H04L9/00

CPC分类号： H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

摘要： A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key.

摘要翻译： 提取单元（a）从微处理器的指令高速缓冲存储器获取指令数据块; （b）使用数据实体在块上执行异或以产生明文指令数据; 和（c）将明文指令数据提供给指令译码单元。 在第一种情况下，块包括加密指令数据，数据实体是解密密钥。 在第二种情况下，该块包括未加密的指令数据，并且数据实体为布尔零。 执行（a），（b）和（c）所需的时间在第一和第二实例中是相同的，而不管该块是加密还是未加密。 解密密钥生成器从多个密钥中选择第一和第二密钥，旋转第一密钥，并且基于获取地址的部分，将旋转后的第一密钥加到/从第二密钥中加减乘以产生解密密钥。

公开(公告)号：US20110296206A1

公开(公告)日：2011-12-01

申请号：US13091828

申请日：2011-04-21

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC分类号： G06F21/00

CPC分类号： H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

摘要： A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a target address and an identifier (index into a register file) for identifying key values associated with each of the previous branch and switch key instructions. A fetch unit receives from the BTAC a prediction that the fetch unit fetched a previous branch and switch key instruction and receives the target address and identifier associated with the fetched branch and switch key instruction. The fetch unit also fetches encrypted instruction data at the associated target address and decrypts (via XOR) the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction. If the BTAC predicts correctly, a pipeline flush normally associated with the branch and switch key instruction is avoided.

摘要翻译： 分支目标地址缓存（BTAC）缓存与微处理器先前执行的分支和切换密钥指令相关联的历史信息。 历史信息包括用于识别与先前分支和切换键指令中的每一个相关联的键值的目标地址和标识符（到寄存器文件的索引）。 获取单元从BTAC接收预取，该预测获取单元获取先前的分支并切换密钥指令，并接收与获取的分支和切换键指令相关联的目标地址和标识符。 提取单元还在相关联的目标地址处获取加密指令数据，并且响应于接收到预测，基于由标识符标识的键值来解密（通过XOR）获取的加密指令数据。 如果BTAC正确预测，则避免通常与分支和切换键指令相关联的流水线清除。