公开(公告)号：US08940641B1

公开(公告)日：2015-01-27

申请号：US14019155

申请日：2013-09-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Taejoon Han ,  Hui Peng Koh

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits with improved patterning schemes are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate. Further, the method includes forming a patterned hard mask overlying the interlayer dielectric material. Also, the method forms an organic planarization layer overlying the patterned hard mask and contacting portions of the interlayer dielectric material. The method patterns the organic planarization layer using an extreme ultraviolet (EUV) lithography process. The method also includes etching the interlayer dielectric material using the patterned hard mask and organic planarization layer as a mask to form vias in the interlayer dielectric material.

Abstract translation: 提供了具有改进的图案化方案的集成电路制造方法。 在一个实施例中，一种用于制造集成电路的方法包括沉积覆盖在半导体衬底上的层间电介质材料。 此外，该方法包括形成覆盖层间电介质材料的图案化硬掩模。 此外，该方法形成覆盖图案化的硬掩模和接触层间电介质材料的部分的有机平坦化层。 该方法使用极紫外（EUV）光刻工艺对有机平面化层进行图案化。 该方法还包括使用图案化硬掩模和有机平坦化层作为掩模蚀刻层间电介质材料，以在层间电介质材料中形成通路。

公开(公告)号：US09252061B2

公开(公告)日：2016-02-02

申请号：US14243491

申请日：2014-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Chan Seob Cho ,  Paul Ackmann ,  Jung Yu Hsieh ,  Hui Peng Koh

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/306 ,  H01L27/088

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

公开(公告)号：US09368453B2

公开(公告)日：2016-06-14

申请号：US14948476

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Chan Seob Cho ,  Paul Ackmann ,  Jung Yu Hsieh ,  Hui Peng Koh

IPC: H01L23/544 ,  H01L29/49

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

Abstract translation: 提供了基于覆盖标记的形状和所得到的装置在有源层区域上形成虚拟结构和覆盖标记保护区域的方法。 实施例包括确定重叠标记的尺寸和形状; 基于覆盖标记的形状确定覆盖标记保护区的大小和形状; 基于重叠标记的形状确定多个虚拟结构的形状; 基于覆盖标记和多个虚拟结构的尺寸和形状来确定活动层区域的尺寸和形状; 在半导体衬底的有源层中形成有源层区; 在所述半导体衬底的多晶硅层中的所述有源层区域上形成所述覆盖标记和所述多个虚设结构; 并平坦化多层。

公开(公告)号：US08911920B2

公开(公告)日：2014-12-16

申请号：US13840790

申请日：2013-03-15

Applicant: GlobalFoundries, Inc.

Inventor： Sudharshanan Raghunathan ,  Pawitter Mangat ,  Hui Peng Koh

IPC: G03F1/44 ,  G03F1/22 ,  G03F7/20

CPC classification number: G03F7/2022 ,  G03F1/22

Abstract: A method for fabricating integrated circuits includes fabricating an EUV mask by providing a photomask having a border region. A photoresist is formed over the photomask and has a border region overlying the border region of the photomask. The method exposes an inner portion and an outer portion of the photoresist border region. The method removes the inner portion and the outer portion to expose the border region of the photomask. The border region of the photomask is etched using the photoresist as a mask to form the EUV mask with a non-reflective border. The photoresist is removed from the EUV mask. The method includes forming another photoresist over a partially-fabricated integrated circuit layer and patterning the photoresist by exposure to EUV light reflected from the EUV mask to expose portions of the partially-fabricated integrated circuit layer. Portions of the partially-fabricated integrated circuit layer and the photoresist are removed.

Abstract translation: 制造集成电路的方法包括通过提供具有边界区域的光掩模来制造EUV掩模。 在光掩模上形成光致抗蚀剂，并且具有覆盖在光掩模的边界区域上的边界区域。 该方法曝光光刻胶边界区域的内部部分和外部部分。 该方法移除内部部分和外部部分以暴露光掩模的边界区域。 使用光致抗蚀剂作为掩模蚀刻光掩模的边界区域，以形成具有非反射边界的EUV掩模。 从EUV掩模中去除光致抗蚀剂。 该方法包括在部分制造的集成电路层上形成另一光致抗蚀剂，并通过暴露于从EUV掩模反射的EUV光来图案化光致抗蚀剂，以暴露部分制造的集成电路层的部分。 去除部分制造的集成电路层和光致抗蚀剂的部分。

公开(公告)号：US20140272677A1

公开(公告)日：2014-09-18

申请号：US13840790

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sudharshanan Raghunathan ,  Pawitter Mangat ,  Hui Peng Koh

IPC: G03F7/20 ,  G03F1/22

CPC classification number: G03F7/2022 ,  G03F1/22

Abstract: A method for fabricating integrated circuits includes fabricating an EUV mask by providing a photomask having a border region. A photoresist is formed over the photomask and has a border region overlying the border region of the photomask. The method exposes an inner portion and an outer portion of the photoresist border region. The method removes the inner portion and the outer portion to expose the border region of the photomask. The border region of the photomask is etched using the photoresist as a mask to form the EUV mask with a non-reflective border. The photoresist is removed from the EUV mask. The method includes forming another photoresist over a partially-fabricated integrated circuit layer and patterning the photoresist by exposure to EUV light reflected from the EUV mask to expose portions of the partially-fabricated integrated circuit layer. Portions of the partially-fabricated integrated circuit layer and the photoresist are removed.

Abstract translation: 制造集成电路的方法包括通过提供具有边界区域的光掩模来制造EUV掩模。 在光掩模上形成光致抗蚀剂，并且具有覆盖在光掩模的边界区域上的边界区域。 该方法曝光光刻胶边界区域的内部部分和外部部分。 该方法移除内部部分和外部部分以暴露光掩模的边界区域。 使用光致抗蚀剂作为掩模蚀刻光掩模的边界区域，以形成具有非反射边界的EUV掩模。 从EUV掩模中去除光致抗蚀剂。 该方法包括在部分制造的集成电路层上形成另一光致抗蚀剂，并通过暴露于从EUV掩模反射的EUV光来图案化光致抗蚀剂，以暴露部分制造的集成电路层的部分。 去除部分制造的集成电路层和光致抗蚀剂的部分。