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Patent Agency Ranking
公开(公告)号：US10678287B2
公开(公告)日：2020-06-09
申请号：US16159831
申请日：2018-10-15
Applicant: GLOBALFOUNDRIES INC.
Inventor： Arif A. Siddiqi , Juhan Kim , Mahbub Rashed
Abstract: Embodiments of the disclosure provide a circuit structure for producing a full range biasing voltage including: a logic control node; first and second voltage generators, coupled to the logic control node, the first and second voltage generators configured to generate a positive voltage output at a positive voltage node and a negative voltage output at a negative voltage node; first and second multiplexer cells, coupled to the logic control node, configured to multiplex the positive voltage level received from the first or the second positive voltage node and the negative voltage level received from the first or the second negative voltage node to provide a multiplexed output; and an output node coupled to each of the first multiplexer cell and the second multiplexer cell configured to receive the multiplexed output to provide a biasing voltage range to at least one transistor having a back-gate terminal.
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公开(公告)号：US20200159270A1
公开(公告)日：2020-05-21
申请号：US16196183
申请日：2018-11-20
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ulrich G. Hensel , Jurgen Faul , Arif A. Siddiqi
IPC: G05F3/16
Abstract: Embodiments of the present disclosure provide a circuit structure including: a first tap node, a first operational element coupled to the first tap node, the first operational element including at least one transistor having a back-gate, a second tap node coupled to the first operational unit, a second operational element coupled to the second tap node, the second operational element including at least one transistor having a back-gate, and a first back-gate biasing voltage regulator coupled to the second operational element and the first tap node. The first back-gate biasing voltage regulator is configured to supply the at least one transistor of the second operational element with a back-gate biasing voltage level that is different than a voltage level available to the second operational element from the second tap node.
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公开(公告)号：US20200117226A1
公开(公告)日：2020-04-16
申请号：US16159831
申请日：2018-10-15
Applicant: GLOBALFOUNDRIES INC.
Inventor： Arif A. Siddiqi , Juhan Kim , Mahbub Rashed
Abstract: Embodiments of the disclosure provide a circuit structure for producing a full range biasing voltage including: a logic control node; first and second voltage generators, coupled to the logic control node, the first and second voltage generators configured to generate a positive voltage output at a positive voltage node and a negative voltage output at a negative voltage node; first and second multiplexer cells, coupled to the logic control node, configured to multiplex the positive voltage level received from the first or the second positive voltage node and the negative voltage level received from the first or the second negative voltage node to provide a multiplexed output; and an output node coupled to each of the first multiplexer cell and the second multiplexer cell configured to receive the multiplexed output to provide a biasing voltage range to at least one transistor having a back-gate terminal.
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公开(公告)号：US10775826B2
公开(公告)日：2020-09-15
申请号：US16196183
申请日：2018-11-20
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ulrich G. Hensel , Jurgen Faul , Arif A. Siddiqi
IPC: G05F3/16
Abstract: Embodiments of the present disclosure provide a circuit structure including: a first tap node, a first operational element coupled to the first tap node, the first operational element including at least one transistor having a back-gate, a second tap node coupled to the first operational unit, a second operational element coupled to the second tap node, the second operational element including at least one transistor having a back-gate, and a first back-gate biasing voltage regulator coupled to the second operational element and the first tap node. The first back-gate biasing voltage regulator is configured to supply the at least one transistor of the second operational element with a back-gate biasing voltage level that is different than a voltage level available to the second operational element from the second tap node.
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公开(公告)号：US10303196B1
公开(公告)日：2019-05-28
申请号：US15966300
申请日：2018-04-30
Applicant: GLOBALFOUNDRIES INC.
Inventor： Navneet Jain , Arif A. Siddiqi , Mahbub Rashed
Abstract: Disclosed is a voltage generator that includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit is selectively operable in a single trimming mode enabling positive trimming only or in a dual trimming mode that shifts the voltage range downward enabling a somewhat smaller amount of positive trimming and also some negative trimming. The second voltage generation circuit is selectively operable in a single trimming mode enabling negative trimming only or in a dual trimming mode that shifts the voltage range upward enabling a somewhat smaller amount of negative trimming and also some positive trimming. Also disclosed is an integrated circuit (IC) chip that incorporates one or more such voltage generators for back-biasing the field effect transistors in one or more circuit blocks, respectively.
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