公开(公告)号：US09490897B2

公开(公告)日：2016-11-08

申请号：US14538170

申请日：2014-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Casimer M. DeCusatis ,  Rajaram B. Krishnamurthy ,  Michael Onghena ,  Anuradha Rao

IPC: H04B10/2575 ,  H04B10/25 ,  G02B6/00 ,  H01L21/00 ,  H01L25/00 ,  H05K1/18

CPC classification number: H04B10/2575 ,  G02B6/00 ,  G02B6/43 ,  H01L21/00 ,  H01L25/00 ,  H01L2924/0002 ,  H01S5/02423 ,  H01S5/423 ,  H04B10/2504 ,  H05K1/181 ,  H05K2201/10515 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Fabricating preassembled optoelectronic interconnect structures is provided, which have an optical waveguide link with first and second optoelectronic circuits attached to first and second ends of the waveguide link. The optoelectronic circuits include active optical componentry which facilitates optical signal communication across the optical waveguide link. Further, first and second pluralities of electrical contacts are associated with the first and second optoelectronic circuits, respectively, to facilitate electrically, operatively connecting the interconnect structure between first and second components of an electronic assembly as, for instance, a single, field-replaceable unit. The first and second components of the electronic assembly may be, for instance, stacked electronic components of the electronic assembly, or laterally offset components of a substantially planar electronic assembly.

Abstract translation: 提供了制造预组装的光电互连结构，其具有光波导链路，第一和第二光电子电路连接到波导链路的第一和第二端。 光电子电路包括促进光波导链路上的光信号通信的有源光学组件。 此外，第一和第二多个电触头分别与第一和第二光电子电路相关联，以便于电气，电连接结构在电子组件的第一和第二部件之间的电连接，例如，单个现场可更换 单元。 电子组件的第一和第二部件可以是例如电子组件的堆叠的电子部件或基本上平面的电子组件的横向偏移的部件。

公开(公告)号：US09225483B2

公开(公告)日：2015-12-29

申请号：US13875235

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Casimer M. DeCusatis ,  Mircea Gusat ,  Keshav G. Kamble ,  Mohanraj Krishnaraj ,  Cyriel J. Minkenberg

IPC: H04L5/00 ,  H04L12/46 ,  H04L12/28 ,  H04L12/54 ,  H04L12/931

CPC classification number: H04L5/0032 ,  H04L12/28 ,  H04L12/4641 ,  H04L12/56 ,  H04L49/354

Abstract: In one embodiment, a system includes processor; and logic integrated with and/or executable by the processor, the logic being adapted to: assign a VLAN type to each of a plurality of VLANs of an architecture; generate a VLAN list type-length-value (vTLV) message; and transmit information to resources based at least in part on the vTLV message, wherein the resources comprise at least one virtual switch and one or more of: at least one physical switch; at least one virtual port; at least one physical port; at least one virtual machine; at least one converged network adapter (CNA); and at least one fiber channel forwarder (FCF).

Abstract translation: 在一个实施例中，系统包括处理器; 以及与所述处理器集成和/或可执行的逻辑，所述逻辑适于：为架构的多个VLAN中的每一个分配VLAN类型; 生成VLAN列表类型长度值（vTLV）消息; 以及至少部分地基于所述vTLV消息将信息发送到资源，其中所述资源包括至少一个虚拟交换机和以下中的一个或多个：至少一个物理交换机; 至少一个虚拟端口; 至少一个物理端口; 至少一个虚拟机; 至少一个融合网络适配器（CNA）; 和至少一个光纤通道转发器（FCF）。