公开(公告)号：US20180190817A1

公开(公告)日：2018-07-05

申请号：US15393400

申请日：2016-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  David Paul BRUNCO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/66795

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US20200258789A9

公开(公告)日：2020-08-13

申请号：US16007023

申请日：2018-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  David Paul BRUNCO

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L27/088

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US20190385914A1

公开(公告)日：2019-12-19

申请号：US16007023

申请日：2018-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  David Paul BRUNCO

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L27/088

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.