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1.发明授权Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations 有权具有多个高速缓存的三维处理系统可以根据多于一组的规则和/或配置进行分区，联合和管理公开(公告)号：US09336144B2
公开(公告)日：2016-05-10
申请号：US13950538
申请日：2013-07-25
Applicant: GLOBALFOUNDRIES INC.
Inventor： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan K. Kailas
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0813 , G06F12/0893 , G06F2212/601 , Y02D10/13
Abstract: Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.
Abstract translation: 提供具有多层联结芯片的三维处理系统，其中一个或多个芯片层包括在多个芯片层上共享高速缓存层次的处理器核心。 高速缓存可以根据各种规则和配置进行分区，联合和管理。
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公开(公告)号：US09257152B2
公开(公告)日：2016-02-09
申请号：US13673262
申请日：2012-11-09
Applicant: GLOBALFOUNDRIES INC.
Inventor： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan K. Kailas
CPC classification number: G11C5/063 , G11C5/025 , H01L27/0688
Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.
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