公开(公告)号：US09916415B2

公开(公告)日：2018-03-13

申请号：US15095239

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Frederick G. Anderson ,  Michael L. Gautsch ,  Jean-Marc Petillat ,  Philippe Ramos ,  Randy L. Wolf ,  Jiansheng Xu

IPC: G06F17/50 ,  H01L27/12

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5036 ,  G06F2217/12 ,  G06F2217/84 ,  H01L27/1211

Abstract: Disclosed are embodiments for modeling integrated circuit (IC) performance. In these embodiments, a parasitic extraction process is performed to generate a netlist that, not only accounts for various parasitics within the IC, but also accounts for substrate-generated signal distortions (e.g., substrate-generated harmonic signal distortions) that occur within the IC. During this netlist extraction process, the design layout of the IC is analyzed to identify parasitics that are to be represented in the netlist and to also identify any circuit elements with output signals that are subject to substrate-generated signal distortions. When such circuit elements are identified, signal distortion models, which were previously empirically determined and stored in a model library, which correspond to the identified circuit elements, and which account for the signal distortions, are selected from the model library and incorporated into the netlist. Simulations are subsequently performed using this netlist to generate a performance model for the IC.