Abstract:
Disclosed are embodiments for modeling integrated circuit (IC) performance. In these embodiments, a parasitic extraction process is performed to generate a netlist that, not only accounts for various parasitics within the IC, but also accounts for substrate-generated signal distortions (e.g., substrate-generated harmonic signal distortions) that occur within the IC. During this netlist extraction process, the design layout of the IC is analyzed to identify parasitics that are to be represented in the netlist and to also identify any circuit elements with output signals that are subject to substrate-generated signal distortions. When such circuit elements are identified, signal distortion models, which were previously empirically determined and stored in a model library, which correspond to the identified circuit elements, and which account for the signal distortions, are selected from the model library and incorporated into the netlist. Simulations are subsequently performed using this netlist to generate a performance model for the IC.
Abstract:
A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.
Abstract:
A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.
Abstract:
A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.