Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory
    1.
    发明授权
    Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory 有权
    用于嵌入式电荷陷阱多时间可编程只读存储器的字线解码器电路

    公开(公告)号:US09503091B2

    公开(公告)日:2016-11-22

    申请号:US14084641

    申请日:2013-11-20

    Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage. The switch includes a series of gated diodes from VWLL with a wordline low protection voltage of VWLL_PR generated by raising VWLL determined by the gated diodes by the threshold voltage, resulting in controlling the WL swing using thin-oxide devices.

    Abstract translation: 用于嵌入式多时间只读存储器的字线解码器电路,其包括耦合到每行中的多个字线的多个NMOS存储器单元。 字线解码器电路通过将升高的字线电压(EWLH)施加到编程模式中,通过模式相关字线高电压(VWLH)和字线低电压(VWLL)捕获电荷来控制目标NMOS存储器阵列的电荷陷阱行为 多个WL中的一个,同时通过向整个阵列施加负的字线电压(NWLL)而以复位模式捕获电荷。 通过在编程模式下将EWLH耦合到VWLH来切换模式相关的电压控制,否则将VDD置于VWLH,而在复位模式下将NWLL耦合到VWLL,否则将GND接地VWLL。 该开关包括来自VWLH的多个门控二极管,通过降低由门控二极管确定的VWLH产生的VWLH_PR的字线高保护电压达到阈值电压。 该开关包括一系列来自VWLL的门控二极管,通过将由门控二极管确定的VWLL提高阈值电压而产生的字线低VWLL_PR的保护电压,从而使用薄氧化物器件控制WL摆幅。

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