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    Data-dependent self-biased differential sense amplifier
    4.
    发明授权
    Data-dependent self-biased differential sense amplifier 有权
    数据相关的自偏置差分读出放大器

    公开(公告)号：US09460760B2

    公开(公告)日：2016-10-04

    申请号：US14604009

    申请日：2015-01-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Balaji Jayaraman ,  Thejas Kempanna ,  Toshiaki Kirihata ,  Ramesh Raghavan ,  Krishnan S. Rengarajan ,  Rajesh R. Tummuru

    IPC: G11C7/06 ,  G11C7/08

    CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C11/401 ,  G11C11/4091 ,  G11C2211/4013

    Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.

    Abstract translation: 一种操作双晶体管单比特多时间可编程存储器单元以提供小信号的高增益感测方案的系统和方法。 存储单元包括一对第一晶体管和提供差分信号输出的第二晶体管。 存储单元的第一晶体管耦合具有第一电流源负载晶体管的第一电路支路，而第二晶体管耦合具有第二电流源负载晶体管的第二电路支路。 编程值由第一或第二晶体管之一中的电压阈值偏移来表示。 反馈电路接收差分信号的第一信号或第二信号中的一个，并且响应地产生反馈信号，该反馈信号被同时施加以偏置每个第一和第二电路腿中的每个电流源负载晶体管，以放大 差分信号输出之间的电压差。

    Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory
    6.
    发明授权
    Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory 有权
    用于嵌入式电荷陷阱多时间可编程只读存储器的字线解码器电路

    公开(公告)号：US09503091B2

    公开(公告)日：2016-11-22

    申请号：US14084641

    申请日：2013-11-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Toshiaki Kirihata ,  Derek H. Leu ,  Ming Yin

    IPC: G11C11/56 ,  G11C16/08 ,  H03K19/0175 ,  G11C16/04 ,  G11C16/12 ,  G06F17/50

    CPC classification number: H03K19/017509 ,  G06F17/5045 ,  G06F2217/78 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  Y02E60/76 ,  Y04S40/22

    Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage. The switch includes a series of gated diodes from VWLL with a wordline low protection voltage of VWLL_PR generated by raising VWLL determined by the gated diodes by the threshold voltage, resulting in controlling the WL swing using thin-oxide devices.

    Abstract translation: 用于嵌入式多时间只读存储器的字线解码器电路，其包括耦合到每行中的多个字线的多个NMOS存储器单元。 字线解码器电路通过将升高的字线电压（EWLH）施加到编程模式中，通过模式相关字线高电压（VWLH）和字线低电压（VWLL）捕获电荷来控制目标NMOS存储器阵列的电荷陷阱行为 多个WL中的一个，同时通过向整个阵列施加负的字线电压（NWLL）而以复位模式捕获电荷。 通过在编程模式下将EWLH耦合到VWLH来切换模式相关的电压控制，否则将VDD置于VWLH，而在复位模式下将NWLL耦合到VWLL，否则将GND接地VWLL。 该开关包括来自VWLH的多个门控二极管，通过降低由门控二极管确定的VWLH产生的VWLH_PR的字线高保护电压达到阈值电压。 该开关包括一系列来自VWLL的门控二极管，通过将由门控二极管确定的VWLL提高阈值电压而产生的字线低VWLL_PR的保护电压，从而使用薄氧化物器件控制WL摆幅。

    Method for defining a default state of a charge trap based memory cell
    8.
    发明授权
    Method for defining a default state of a charge trap based memory cell 有权
    用于定义基于电荷陷阱的存储器单元的默认状态的方法

    公开(公告)号：US09324430B2

    公开(公告)日：2016-04-26

    申请号：US14265409

    申请日：2014-04-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sheikh Sabiq Chishti ,  Toshiaki Kirihata ,  Krishnan S. Rengarajan ,  Deepal Wehella-Gamage

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/28

    CPC classification number: G11C16/0466 ,  G11C11/5692 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C17/12 ,  G11C17/14 ,  G11C17/18

    Abstract: A method of generating a default state in an embedded Multi-Time-Programmable-Read-Only-Memory for a high-performance logic technology consisting of a plurality of memory cells featuring a charge trap, each having a first and a second NMOS transistor. The first and second NMOS transistors use a different mask having different threshold voltages. The second NMOS threshold voltage is adjusted to a middle point of the threshold voltage of the first NMOS with or without trapping the charge. When the charge is not trapped by the first NMOS, the NMOS threshold is lowered to the second NMOS, thereby generating a default state. When the charge is trapped to the first NMOS, the NMOS threshold is higher than the second NMOS, generating a second state. Moreover, a reference voltage generation can use two arrays, each consisting of memory cells and reference memory cells such that a default state can be generated for a single transistor per memory cell.

    Abstract translation: 一种用于由具有电荷陷阱的多个存储单元组成的高性能逻辑技术的嵌入式多时间可编程只读存储器中产生默认状态的方法，每个具有第一和第二NMOS晶体管。 第一和第二NMOS晶体管使用具有不同阈值电压的不同掩模。 第二NMOS阈值电压被调整到第一NMOS的阈值电压的中点，不管是否捕获电荷。 当电荷未被第一NMOS捕获时，NMOS阈值降低到第二NMOS，从而产生默认状态。 当电荷被俘获到第一NMOS时，NMOS阈值高于第二NMOS，产生第二状态。 此外，参考电压产生可以使用两个阵列，每个阵列由存储器单元和参考存储器单元组成，使得可以为每个存储器单元的单个晶体管产生默认状态。

    Disturb free bitcell and array
    9.
    发明授权
    Disturb free bitcell and array 有权
    免打扰bitcell和阵列

    公开(公告)号：US09589658B1

    公开(公告)日：2017-03-07

    申请号：US14828770

    申请日：2015-08-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Navin Agarwal ,  Aditya S. Auyisetty ,  Balaji Jayaraman ,  Thejas Kempanna ,  Toshiaki Kirihata ,  Ramesh Raghavan ,  Krishnan S. Rengarajan ,  Rajesh R. Tummuru ,  Jay M. Shah ,  Janakiraman Viraraghavan

    IPC: G11C16/22 ,  G11C16/34

    CPC classification number: G11C16/3427 ,  G11C7/02 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C17/14 ,  G11C17/18

    Abstract: Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.

    Abstract translation: 提供了包括单元阵列的存储器的方法。 存储器包括连接到位线和节点并由字线控制的单元阵列的第一器件和单元阵列的第二器件，其包括连接到源极线和该节点的第三器件，以及 由字线控制，第四器件连接在字线和节点之间。 在存储器中，响应于单元阵列中的另一个字线被激活并且字线未被激活以保持第一器件处于未编程状态，第三器件隔离并漂浮该节点，使得栅极的电压电平 第一器件的源极被第四器件钳位到零电压附近的电压电平。

    Rebalancing in twin cell memory schemes to enable multiple writes
    10.
    发明授权
    Rebalancing in twin cell memory schemes to enable multiple writes 有权
    重新平衡双胞细胞存储器方案以启用多次写入

    公开(公告)号：US09418745B1

    公开(公告)日：2016-08-16

    申请号：US14661383

    申请日：2015-03-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xiang Chen ,  Toshiaki Kirihata ,  Derek H. Leu ,  Dan Moy

    IPC: G11C16/04 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26

    CPC classification number: G11C16/14 ,  G11C16/10 ,  G11C16/20 ,  G11C16/26

    Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.

    Abstract translation: 一种操作双晶体管，多时间可编程存储器（MTPM）存储单元的系统和方法，其确保在每个写周期之后读取的位值的精确再现性。 每个多时间可编程存储器单元包括第一晶体管和第二晶体管的串联连接。 该方法包括将选择存储单元位置处的写入电路写入到一个或多个选择存储单元的初始位值。 然后，使用写入电路，执行在每个选择存储单元处与一个或多个第一晶体管或第二晶体管相关联的参数的状态的再平衡。 然后，在每个重新平衡选择存储单元处执行擦除周期，写入的初始位值。 在一个实施例中，可以在重新平衡之前首先执行擦除循环。 在每个位值写周期之前执行重新平衡和擦除。

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