公开(公告)号：US09418745B1

公开(公告)日：2016-08-16

申请号：US14661383

申请日：2015-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiang Chen ,  Toshiaki Kirihata ,  Derek H. Leu ,  Dan Moy

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/10 ,  G11C16/20 ,  G11C16/26

Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.

Abstract translation: 一种操作双晶体管，多时间可编程存储器（MTPM）存储单元的系统和方法，其确保在每个写周期之后读取的位值的精确再现性。 每个多时间可编程存储器单元包括第一晶体管和第二晶体管的串联连接。 该方法包括将选择存储单元位置处的写入电路写入到一个或多个选择存储单元的初始位值。 然后，使用写入电路，执行在每个选择存储单元处与一个或多个第一晶体管或第二晶体管相关联的参数的状态的再平衡。 然后，在每个重新平衡选择存储单元处执行擦除周期，写入的初始位值。 在一个实施例中，可以在重新平衡之前首先执行擦除循环。 在每个位值写周期之前执行重新平衡和擦除。

公开(公告)号：US09355739B2

公开(公告)日：2016-05-31

申请号：US14084644

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pamela Castalino ,  Toshiaki Kirihata ,  Derek H. Leu

IPC: G11C11/56 ,  G11C16/04 ,  G11C17/18 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C17/18 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices. The bitline circuits having mode and bank access dependent bitline circuit further enables a single device memory array, by using two arrays, wherein said one of the array is used for reference to the other array using an open bitline architecture.

Abstract translation: 嵌入式多时间只读存储器的位线电路，包括耦合到每行中的多个字线，每列中的位线和源极线的多个NMOS存储器单元。 更具体地，位线电路通过模式相关的位线下拉电路来控制目标NMOS存储器阵列的电荷陷阱行为，从而将位线强烈地放电到GND，以在编程模式下有效地捕获电荷，并将位线弱化 GND产生位线电压以检测电荷陷阱状态。 模式相关电路通过使用至少两个NMOS来切换器件强度，使用读取模式下的脉冲栅极控制或使用模拟电压来限制位线电流来实现。 所提出的方法还包括保护装置，允许使用薄氧化物装置的所有位线控制电路。 具有模式和与银行接入相关的位线电路的位线电路还通过使用两个阵列使单个设备存储器阵列进一步启用，其中阵列中的所述一个使用打开的位线架构用于引用另一阵列。

公开(公告)号：US09503091B2

公开(公告)日：2016-11-22

申请号：US14084641

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Toshiaki Kirihata ,  Derek H. Leu ,  Ming Yin

IPC: G11C11/56 ,  G11C16/08 ,  H03K19/0175 ,  G11C16/04 ,  G11C16/12 ,  G06F17/50

CPC classification number: H03K19/017509 ,  G06F17/5045 ,  G06F2217/78 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  Y02E60/76 ,  Y04S40/22

Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage. The switch includes a series of gated diodes from VWLL with a wordline low protection voltage of VWLL_PR generated by raising VWLL determined by the gated diodes by the threshold voltage, resulting in controlling the WL swing using thin-oxide devices.

Abstract translation: 用于嵌入式多时间只读存储器的字线解码器电路，其包括耦合到每行中的多个字线的多个NMOS存储器单元。 字线解码器电路通过将升高的字线电压（EWLH）施加到编程模式中，通过模式相关字线高电压（VWLH）和字线低电压（VWLL）捕获电荷来控制目标NMOS存储器阵列的电荷陷阱行为 多个WL中的一个，同时通过向整个阵列施加负的字线电压（NWLL）而以复位模式捕获电荷。 通过在编程模式下将EWLH耦合到VWLH来切换模式相关的电压控制，否则将VDD置于VWLH，而在复位模式下将NWLL耦合到VWLL，否则将GND接地VWLL。 该开关包括来自VWLH的多个门控二极管，通过降低由门控二极管确定的VWLH产生的VWLH_PR的字线高保护电压达到阈值电压。 该开关包括一系列来自VWLL的门控二极管，通过将由门控二极管确定的VWLL提高阈值电压而产生的字线低VWLL_PR的保护电压，从而使用薄氧化物器件控制WL摆幅。

公开(公告)号：US09497027B2

公开(公告)日：2016-11-15

申请号：US14293306

申请日：2014-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiang Chen ,  Derek H. Leu ,  Toshiaki Kirihata ,  Sami Rosenblatt

IPC: G06F11/30 ,  H04L9/32 ,  G11C16/04 ,  G11C17/16 ,  G06F12/14 ,  G09C1/00 ,  G11C7/24 ,  G11C11/56

CPC classification number: H04L9/3278 ,  G06F12/1408 ,  G06F12/1425 ,  G09C1/00 ,  G11C7/24 ,  G11C11/5692 ,  G11C16/0491 ,  G11C16/22 ,  G11C17/16

Abstract: Described are a hardware encryption engine, and secret key registration and authentication system recoverable binary bit using knowing an initial secret key stored in the master system. The secret key is overwritten in each authentication, updating it to the master and encryption engine independently. The secret key over write command can be preferably given to the chip as a CHG, and the non recoverable binary bit from the sense amplifier is used for response.

Abstract translation: 描述了硬件加密引擎，以及使用知道存储在主系统中的初始秘密密钥的秘密密钥注册和认证系统可恢复的二进制位。 每个身份验证中都会覆盖秘密密钥，将其独立更新为主服务器和加密引擎。 秘密密钥写入命令可以优选地作为CHG被提供给芯片，并且来自读出放大器的不可恢复的二进制位用于响应。