公开(公告)号：US20180286982A1

公开(公告)日：2018-10-04

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. KRISHNAN ,  Timothy J. MCARDLE ,  Rinus Tek Po LEE ,  Shishir K. Ray ,  Akshey SEHGAL

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7848 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

公开(公告)号：US20210013109A1

公开(公告)日：2021-01-14

申请号：US16508815

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. KRISHNAN ,  Rinus Tek Po LEE ,  Jiehui SHU ,  Hyung Yoon CHOI

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/67

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.