公开(公告)号：US10727327B2

公开(公告)日：2020-07-28

申请号：US15882053

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rahul Mishra ,  Vibhor Jain ,  Ajay Raman ,  Robert J. Gauthier

IPC: H01L29/749 ,  H01L29/66 ,  H01L29/74 ,  H01L27/02 ,  H01L29/737

Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.

公开(公告)号：US20190237568A1

公开(公告)日：2019-08-01

申请号：US15882053

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rahul Mishra ,  Vibhor Jain ,  Ajay Raman ,  Robert J. Gauthier

IPC: H01L29/749 ,  H01L29/66 ,  H01L29/74

Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.

公开(公告)号：US09263517B2

公开(公告)日：2016-02-16

申请号：US13835463

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Jason E. Cummings ,  Toshiharu Furukawa ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/0649 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203

Abstract: Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

Abstract translation: 各种方面包括极薄的绝缘体上半导体（ETSOI）层。 在一个实施例中，ETSOI层包括限定多个不同的绝缘体上半导体（SOI）区域的多个浅沟槽隔离（STI），不同的SOI区域具有至少三个不同的厚度; 位于不同SOI区域内的至少一个凹部; 和在所述至少一个凹部上的氧化物盖。