公开(公告)号：US09886998B2

公开(公告)日：2018-02-06

申请号：US15175466

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Qing Li ,  Wei Zhao ,  Xiaoli Hu

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/067

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed.

公开(公告)号：US10510385B2

公开(公告)日：2019-12-17

申请号：US15903826

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoli Hu ,  Wei Zhao ,  Hao Pu

IPC: G11C7/12 ,  G11C11/419

Abstract: A structure includes a write driver circuit configured to drive both a true bitline side and a complement bitline side up to a power supply and down to ground such that one of the true bitline side and the complement bitline side is driven to ground and another of the true bitline side and the complement bitline side is driven to a high level at a same time and before a precharge below a level of the power supply of the one of the true bitline side and the complement bitline side.

公开(公告)号：US10446233B2

公开(公告)日：2019-10-15

申请号：US15684492

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Qing Li ,  Xiaoli Hu ,  Wei Zhao ,  Jieyao Liu

IPC: G11C15/04 ,  G11C11/419 ,  G11C7/06 ,  G11C7/12

Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.

公开(公告)号：US09893765B1

公开(公告)日：2018-02-13

申请号：US15464397

申请日：2017-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Xiaoli Hu ,  Wei Zhao ,  Chao Meng ,  Xiaoxiao Li

IPC: H04B3/54 ,  H04B1/52 ,  H04B1/04

CPC classification number: H04B3/54 ,  H04B1/04 ,  H04B1/52

Abstract: Devices include a primary transmission system, and first and second duplicate (dummy or non-transmitting) transmission systems. The primary transmission system includes a primary transmitter circuit receiving a data signal, a primary transmission line connected to the primary transmitter circuit, and a primary receiver circuit connected to the primary transmission line. The first duplicate transmission system is connected to the primary transmitter circuit, and supplies a transmission timing control signal to the primary transmitter circuit. The primary transmitter circuit stops transmitting (e.g., stops reducing the voltage of the primary transmission line) when the transmission timing control signal is received. The second duplicate transmission system is connected to the primary receiver circuit, and supplies an output timing control signal to the primary receiver circuit, and the primary receiver circuit outputs the data signal when the output timing control signal is received.