公开(公告)号：US10446233B2

公开(公告)日：2019-10-15

申请号：US15684492

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Qing Li ,  Xiaoli Hu ,  Wei Zhao ,  Jieyao Liu

IPC: G11C15/04 ,  G11C11/419 ,  G11C7/06 ,  G11C7/12

Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.

公开(公告)号：US20190273148A1

公开(公告)日：2019-09-05

申请号：US16415519

申请日：2019-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10325811B2

公开(公告)日：2019-06-18

申请号：US15794600

申请日：2017-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco ,  Wei Zhao ,  Haiting Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.

公开(公告)号：US09984933B1

公开(公告)日：2018-05-29

申请号：US15723416

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Wei Zhao ,  Todd B. Abrams ,  Jiehui Shu ,  Jinping Liu ,  Scott Beasor

IPC: H01L21/311 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/28123 ,  H01L21/30625 ,  H01L21/823481 ,  H01L29/785

Abstract: A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is formed on the hardmask elements and the fins in processing that forms the layer of silicon thicker on the hardmask elements relative to the fins. An isolation material is formed on the layer of silicon to leave the isolation material filling spaces between the fins. The isolation material and the layer of silicon are annealed to consume relatively thinner portions of the layer of silicon and leave the layer of silicon on the hardmask elements as silicon elements. A chemical mechanical polishing (CMP) is performed on the isolation material to make the isolation material planar with the silicon elements. A first etching agent removes the silicon elements on the hardmask elements, and a second chemical agent removes the hardmask elements.

公开(公告)号：US09893765B1

公开(公告)日：2018-02-13

申请号：US15464397

申请日：2017-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Xiaoli Hu ,  Wei Zhao ,  Chao Meng ,  Xiaoxiao Li

IPC: H04B3/54 ,  H04B1/52 ,  H04B1/04

CPC classification number: H04B3/54 ,  H04B1/04 ,  H04B1/52

Abstract: Devices include a primary transmission system, and first and second duplicate (dummy or non-transmitting) transmission systems. The primary transmission system includes a primary transmitter circuit receiving a data signal, a primary transmission line connected to the primary transmitter circuit, and a primary receiver circuit connected to the primary transmission line. The first duplicate transmission system is connected to the primary transmitter circuit, and supplies a transmission timing control signal to the primary transmitter circuit. The primary transmitter circuit stops transmitting (e.g., stops reducing the voltage of the primary transmission line) when the transmission timing control signal is received. The second duplicate transmission system is connected to the primary receiver circuit, and supplies an output timing control signal to the primary receiver circuit, and the primary receiver circuit outputs the data signal when the output timing control signal is received.

公开(公告)号：US10600914B2

公开(公告)日：2020-03-24

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US10373877B1

公开(公告)日：2019-08-06

申请号：US15986390

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Hui Zang ,  Wei Zhao ,  Yue Zhong ,  Guowei Xu ,  Laertis Economikos ,  Jerome Ciavatti ,  Scott Beasor

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.

公开(公告)号：US20190097019A1

公开(公告)日：2019-03-28

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66795

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10707175B2

公开(公告)日：2020-07-07

申请号：US15985838

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Minghao Tang ,  Rui Chen ,  Dongyue Yang ,  Haiting Wang ,  Erik Geiss ,  Scott Beasor

IPC: H01L23/544

Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.

公开(公告)号：US10121788B1

公开(公告)日：2018-11-06

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.