公开(公告)号：US09633915B1

公开(公告)日：2017-04-25

申请号：US15057727

申请日：2016-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dongsuk Park ,  Yue Zhou ,  Mert Karakoy

IPC: H01L21/66 ,  H01J37/28 ,  G01B15/00

CPC classification number: H01J37/28 ,  G03F7/70633 ,  G03F7/70683 ,  H01L22/12

Abstract: Methodologies for using dummy patterns for overlay target design and overlay control are provided. Embodiments include providing a first dummy pattern on a first layer as an outer overlay target for an integrated circuit (IC); providing a pattern associated with a second dummy pattern on a second layer as a target for measuring overlay; and utilizing a scanning electron microscope (SEM) to obtain an overlay measurement between the first and second dummy patterns.

公开(公告)号：US10733354B2

公开(公告)日：2020-08-04

申请号：US16225199

申请日：2018-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hojin Kim ,  Dongyue Yang ,  Dong-Ick Lee ,  Yue Zhou ,  Jae Ho Joung ,  Gregory Costrini ,  El Mehdi Bazizi ,  Dongsuk Park

IPC: G06F30/398

Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.