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    System and method employing three-dimensional (3D) emulation of in-kerf optical macros
    1.
    发明授权
    System and method employing three-dimensional (3D) emulation of in-kerf optical macros 有权

    公开(公告)号：US10733354B2

    公开(公告)日：2020-08-04

    申请号：US16225199

    申请日：2018-12-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hojin Kim ,  Dongyue Yang ,  Dong-Ick Lee ,  Yue Zhou ,  Jae Ho Joung ,  Gregory Costrini ,  El Mehdi Bazizi ,  Dongsuk Park

    IPC: G06F30/398

    Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.

    Capacitor and contact structures, and formation processes thereof
    2.
    发明授权
    Capacitor and contact structures, and formation processes thereof 有权

    公开(公告)号：US09679959B2

    公开(公告)日：2017-06-13

    申请号：US14837288

    申请日：2015-08-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ki Young Lee ,  Sanggil Bae ,  Jae Ho Joung

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L27/10805

    Abstract: Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.

    Methods of forming a capacitor and contact structures
    5.
    发明授权
    Methods of forming a capacitor and contact structures 有权
    形成电容器和接触结构的方法

    公开(公告)号：US09178009B2

    公开(公告)日：2015-11-03

    申请号：US13648504

    申请日：2012-10-10

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Ki Young Lee ,  Sanggil Bae ,  Jae Ho Joung

    IPC: H01G7/00 ,  H01L49/02

    CPC classification number: H01L28/60 ,  H01L27/10805

    Abstract: Methods of forming a capacitor and contact structures are provided. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.

    Abstract translation: 提供形成电容器和接触结构的方法。 所述方法包括例如在导电结构之上和电容器的下电极之上提供导电材料层; 蚀刻导电材料层以限定导电材料硬掩模和电容器的上电极，导电材料硬掩模至少部分地设置在导电结构之上; 以及形成第一导电接触结构和第二导电接触结构，所述第一导电接触结构延伸穿过所述导电材料硬掩模中的开口并导电地接触所述导电结构，并且所述第二导电接触结构导电地接触所述导电接触结构的下电极之一 电容器或电容器的上电极。

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