公开(公告)号：US20150311293A1

公开(公告)日：2015-10-29

申请号：US14259726

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shiv Kumar MISHRA ,  Zhiqing LI ,  Scott BEASOR ,  Shesh Mani PANDEY

IPC: H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/365 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

Abstract translation: 提供了P型金属氧化物半导体场效应晶体管（pMOSFET），包括pMOSFET的半导体器件和形成pMOSFET的方法。 pMOSFET包括具有与半导体衬底和上表面接触的较低界面的硅 - 锗（SiGe）膜，并且SiGe膜具有梯度硼掺杂分布，其中硼含量在硼的宽度的大部分上向上增加 SiGe膜的下界面与SiGe膜的上表面之间的掺杂SiGe膜。 形成pMOSFET的方法包括：提供半导体衬底; 在半导体衬底上沉积SiGe膜，从而形成与半导体衬底接触的SiGe膜的下界面和SiGe膜的上表面; 并且用硼掺杂SiGe膜以形成具有渐变硼掺杂分布的SiGe膜，其中硼含量在SiGe膜的下界面和SiGe的上表面之间的硼掺杂SiGe膜的宽度的大部分上向上增加 电影。

公开(公告)号：US20180040696A1

公开(公告)日：2018-02-08

申请号：US15227330

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiqing LI ,  Shesh Mani PANDEY ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/22 ,  H01L29/167 ,  H01L29/16 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/2225 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P.