公开(公告)号：US10325848B2

公开(公告)日：2019-06-18

申请号：US16127645

申请日：2018-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L29/49 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US10236253B2

公开(公告)日：2019-03-19

申请号：US15484309

申请日：2017-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/417

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US09818873B2

公开(公告)日：2017-11-14

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V. V. S. Surisetty ,  Mickey H. Yu

IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

公开(公告)号：US09698101B2

公开(公告)日：2017-07-04

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US20160033958A1

公开(公告)日：2016-02-04

申请号：US14449222

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Stan Tsai ,  Charan V. V. S. Surisetty

IPC: G05B19/418

CPC classification number: B24B49/12 ,  B24B37/013 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

Abstract: Disclosed are approaches for determining a processing endpoint using individually measured target spectra. More specifically, one approach includes: measuring a white light (WL) target spectra of a semiconductor device on an individual wafer prior to formation of a polishing/planarization material; inputting the WL target spectra to a WL endpoint algorithm of the semiconductor device following formation of the polishing/planarization material; and determining, using the WL endpoint algorithm, the processing endpoint of the polishing/planarization material of the semiconductor device. In another approach, the endpoint measurement process comprises receiving spectra reflected from the semiconductor device during polishing, and comparing the spectra to the WL target spectra, which is previously stored within a storage device. As such, WL target spectra are measured “as is” (e.g., without simplifications, generalizations, assumptions, etc.) for each wafer to reduce complications inherent with the use of an uncertain and/or estimated target.

Abstract translation: 公开了使用单独测量的目标光谱确定处理端点的方法。 更具体地，一种方法包括：在形成抛光/平坦化材料之前测量单个晶片上的半导体器件的白光（WL）目标光谱; 在形成抛光/平坦化材料之后，将WL目标光谱输入到半导体器件的WL端点算法; 以及使用WL端点算法确定半导体器件的抛光/平坦化材料的处理端点。 在另一种方法中，端点测量过程包括在抛光期间接收从半导体器件反射的光谱，并将光谱与预先存储在存储器件中的WL目标光谱进行比较。 因此，WL目标光谱“按原样”测量（例如，没有简化，概括，假设等），以减少使用不确定和/或估计的目标固有的并发症。