公开(公告)号：US20170358687A1

公开(公告)日：2017-12-14

申请号：US15180422

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kwan-Yong LIM ,  Steven John BENTLEY ,  Daniel CHANEMOUGAME

IPC: H01L29/786 ,  H01L27/24 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20200098913A1

公开(公告)日：2020-03-26

申请号：US16139917

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Andre LABONTE ,  Daniel CHANEMOUGAME

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49

Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

公开(公告)号：US20200083102A1

公开(公告)日：2020-03-12

申请号：US16685648

申请日：2019-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20190214298A1

公开(公告)日：2019-07-11

申请号：US15868479

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20180233412A1

公开(公告)日：2018-08-16

申请号：US15433188

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Nigel CAVE

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823425 ,  H01L21/28518 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

公开(公告)号：US20180061993A1

公开(公告)日：2018-03-01

申请号：US15793545

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kwan-Yong LIM ,  Steven John BENTLEY ,  Daniel CHANEMOUGAME

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L27/24 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.