公开(公告)号：US09673115B2

公开(公告)日：2017-06-06

申请号：US14933107

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Dieter Lipp ,  Stefan Richter

IPC: H01L29/10 ,  H01L21/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L21/283 ,  H01L21/02488 ,  H01L22/34 ,  H01L29/0653 ,  H01L29/78

Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.

公开(公告)号：US20170133287A1

公开(公告)日：2017-05-11

申请号：US14933107

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Dieter Lipp ,  Stefan Richter

IPC: H01L21/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/283 ,  H01L21/02488 ,  H01L22/34 ,  H01L29/0653 ,  H01L29/78

Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.

公开(公告)号：US20140110772A1

公开(公告)日：2014-04-24

申请号：US14075517

申请日：2013-11-08

Applicant: Globalfoundries, Inc.

Inventor： Andreas Kerber ,  Tanya Nigam ,  Dieter Lipp ,  Marc Herden

IPC: H01L27/06

CPC classification number: H01L27/06 ,  H01L27/0629 ,  H01L27/0805

Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.

Abstract translation: 为集成电路提供去耦电容器布置。 该装置包括彼此并联电连接的多个去耦电容器阵列。 每个阵列包括多个去耦电容器和限流元件。 每个阵列的去耦电容彼此并联电连接。 限流元件与多个去耦电容器串联连接。