公开(公告)号：US10811069B2

公开(公告)日：2020-10-20

申请号：US16248279

申请日：2019-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Harsh N. Patel ,  Bipul C. Paul

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L23/528 ,  H01L29/423 ,  H01L21/8238 ,  H01L43/02 ,  H01F10/32

Abstract: Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.

公开(公告)号：US10586581B1

公开(公告)日：2020-03-10

申请号：US16205921

申请日：2018-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Harsh N. Patel ,  Bipul C. Paul ,  Joseph Versaggi

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14 ,  H01L45/00 ,  H01L43/02 ,  H01L43/12

Abstract: Structures for a non-volatile memory and methods for forming and using such structures. A bitcell of the non-volatile memory includes a nonvolatile memory element and a field-effect transistor having a drain region coupled with the nonvolatile memory element, a source region, and a gate electrode. A word line is coupled with the gate electrode of the field-effect transistor, a bit line is coupled with the nonvolatile memory element, and a source line is coupled with the source region of the field-effect transistor. A power supply is configured to supply a negative bias voltage to the bit line in order to provide a first state for writing data to the nonvolatile memory element or to supply the negative bias voltage to the source line in order to provide a second state for writing data to the nonvolatile memory element.

公开(公告)号：US20200227107A1

公开(公告)日：2020-07-16

申请号：US16248279

申请日：2019-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Harsh N. Patel ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L23/528 ,  H01L29/423 ,  H01L21/8238 ,  G11C13/00

Abstract: Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.