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公开(公告)号：US10727108B2
公开(公告)日：2020-07-28
申请号：US16168414
申请日：2018-10-23
Applicant: GLOBALFOUNDRIES Inc.
Inventor： David Pritchard , Heng Yang , Hongru Ren
IPC: H01L21/762 , H01L21/84 , H01L29/08 , H01L21/027 , H01L29/66 , H01L27/12 , H01L21/285 , H01L29/78
Abstract: The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.
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公开(公告)号：US20210057558A1
公开(公告)日：2021-02-25
申请号：US16548518
申请日：2019-08-22
Applicant: GLOBALFOUNDRIES Inc.
Inventor： David Pritchard , Heng Yang , Hongru Ren , Neha Nayyar , Manjunatha Prabhu , Elizabeth Strehlow , Salvatore Cimino
Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.
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