公开(公告)号：US10217633B2

公开(公告)日：2019-02-26

申请号：US15456757

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng Yang ,  Ahmed Hassan ,  Daniel Dechene

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/768

Abstract: A single critical mask process flow and associated structure eliminate the formation of narrow polysilicon defects at the ends of polysilicon gate arrays, and obviate the need to implement complicated ground rules and post-design fill methods to avoid generation of the defects.

公开(公告)号：US10727108B2

公开(公告)日：2020-07-28

申请号：US16168414

申请日：2018-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren

IPC: H01L21/762 ,  H01L21/84 ,  H01L29/08 ,  H01L21/027 ,  H01L29/66 ,  H01L27/12 ,  H01L21/285 ,  H01L29/78

Abstract: The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.

公开(公告)号：US10529704B1

公开(公告)日：2020-01-07

申请号：US16148323

申请日：2018-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Salvatore Cimino ,  David Pritchard ,  Lixia Lei ,  Heng Yang ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

Abstract: One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.

公开(公告)号：US20210057558A1

公开(公告)日：2021-02-25

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US20200328306A1

公开(公告)日：2020-10-15

申请号：US16382184

申请日：2019-04-11

Applicant: GlobalFoundries Inc.

Inventor： Jin Wallner ,  Heng Yang ,  Judson Robert Holt

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088

Abstract: A method of forming a semiconductor device is provided, which includes providing gate structures over an active region and forming a hard mask segment on the active region positioned between a first gate structure and a second gate structure. Cavities are formed in the active region using the gate structures and the hard mask segment as masking features, wherein each cavity has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device. Epitaxial material is grown in the cavities to form substantially uniform epitaxial structures in the active region.