公开(公告)号：US20160378902A1

公开(公告)日：2016-12-29

申请号：US14749909

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ioana C. Graur ,  Ian P. Stobert ,  Dmitry A. Vengertsev

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077

Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

Abstract translation: 可以使用基于已知数据（例如历史热点数据，特征提取和几何图元）训练的生成模型来生成候选布局模式。 可以对生成模型进行采样，以获得可以使用错误优化，设计规则检查，光学邻近检查和其他方法进行排名和修复的候选布局，以确保生成的候选者是可制造的。

公开(公告)号：US10042973B2

公开(公告)日：2018-08-07

申请号：US15281183

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ioana C. Graur ,  Dmitry Vengertsev

IPC: G06F17/50

Abstract: Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule waiver system. The design rule waiver system may process the first design rule to extract a plurality of descriptors that can be perturbed. The design rule waiver system may perturb an attribute associated with at least one of the plurality of descriptors extracted from the first design rule in order to define a second design rule that is satisfied by the plurality of patterns.

公开(公告)号：US10386714B2

公开(公告)日：2019-08-20

申请号：US15401299

申请日：2017-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kriteshwar K. Kohli ,  Mark N. Jobes ,  Ioana C. Graur

IPC: G06F17/50 ,  G03F1/36

Abstract: Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (OPC). Methods according to the disclosure can include: fabricating a circuit using a proposed IC layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (SRAF) from the proposed IC layout; determining the predicting as being correct when the fabricated circuit includes the printed SRAF, or as being incorrect when the fabricated circuit does not include the printed SRAF; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.

公开(公告)号：US20180096093A1

公开(公告)日：2018-04-05

申请号：US15281183

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ioana C. Graur ,  Dmitry Vengertsev

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12

Abstract: Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule waiver system. The design rule waiver system may process the first design rule to extract a plurality of descriptors that can be perturbed. The design rule waiver system may perturb an attribute associated with at least one of the plurality of descriptors extracted from the first design rule in order to define a second design rule that is satisfied by the plurality of patterns.

公开(公告)号：US20180196340A1

公开(公告)日：2018-07-12

申请号：US15401299

申请日：2017-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kriteshwar K. Kohli ,  Mark N. Jobes ,  Ioana C. Graur

IPC: G03F1/36 ,  G06F17/50

CPC classification number: G03F1/36

Abstract: Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (OPC). Methods according to the disclosure can include: fabricating a circuit using a proposed IC layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (SRAF) from the proposed IC layout; determining the predicting as being correct when the fabricated circuit includes the printed SRAF, or as being incorrect when the fabricated circuit does not include the printed SRAF; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.

公开(公告)号：US09690898B2

公开(公告)日：2017-06-27

申请号：US14749909

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ioana C. Graur ,  Ian P. Stobert ,  Dmitry A. Vengertsev

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077

Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.