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    MEMORY BIT CELL FOR REDUCED LAYOUT AREA
    1.
    发明申请
    MEMORY BIT CELL FOR REDUCED LAYOUT AREA 有权
    用于减少布局区域的存储位单元

    公开(公告)号：US20160322367A1

    公开(公告)日：2016-11-03

    申请号：US15140548

    申请日：2016-04-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Juhan KIM ,  Mahbub RASHED

    IPC: H01L27/11 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

    CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

    Abstract: An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

    Abstract translation: 公开了一种用于提供具有小型化位单元的SRAM位单元的方法，没有本地互连层，具有改进的平版印刷可印刷性和使能方法。 实施例包括在M1层中提供包括第一字线，第一位线，第二位线，第一接地线，第二接地线，第二锁存线或其组合的第一颜色结构，其中第一 颜色结构包括比边缘长的侧边缘; 在M1层中提供第二颜色结构，包括第二字线，第一电源线，第二电源线，第一锁存线或其组合，其中第二颜色结构包括比尖端边缘长的侧边缘; 以及形成包括所述第一颜色结构和所述第二颜色结构的位单元，其中相邻的尖端边缘包括第一颜色结构的尖端边缘和第二颜色结构的尖端边缘。

    FORMING GATE TIE BETWEEN ABUTTING CELLS AND RESULTING DEVICE
    2.
    发明申请
    FORMING GATE TIE BETWEEN ABUTTING CELLS AND RESULTING DEVICE 审中-公开
    在细胞和结果设备之间形成门

    公开(公告)号：US20150311122A1

    公开(公告)日：2015-10-29

    申请号：US14263399

    申请日：2014-04-28

    Applicant: Globalfoundries Inc.

    Inventor： Mahbub RASHED ,  Yunfei DENG ,  Juhan KIM ,  Jongwook KYE ,  Suresh VENKATESAN ,  Subramani KENGERI

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

    CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886

    Abstract: Methods for forming abutting FinFET cells with a single dummy gate and continuous fins, and the resulting devices, are disclosed. Embodiments may include forming one or more continuous fins on a substrate, forming gates perpendicular to and over the one or more continuous fins to form a first FinFET cell and a second FinFET cell, and forming source and drain contact lines parallel to and between the gates, wherein a source contact line of the first FinFET cell is adjacent to a drain contact line of the second FinFET cell, and the source contact line and the drain contact line are on opposite sides of a gate.

    Abstract translation: 公开了用于形成具有单个虚拟栅极和连续散热片的邻接FinFET单元的方法以及所得到的器件。 实施例可以包括在基板上形成一个或多个连续的翅片，形成垂直于一个或多个连续翅片上方和上方的栅极以形成第一FinFET单元和第二FinFET单元，以及形成平行于栅极和栅极之间的源极和漏极接触线 ，其中所述第一FinFET单元的源极接触线与所述第二FinFET单元的漏极接触线相邻，并且所述源极接触线和所述漏极接触线位于栅极的相对侧上。

    BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES
    4.
    发明申请
    BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES 有权
    具有双重图案化金属层结构的位电池

    公开(公告)号：US20140332967A1

    公开(公告)日：2014-11-13

    申请号：US14337596

    申请日：2014-07-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Juhan KIM ,  Mahbub RASHED

    IPC: H01L23/538 ,  H01L27/11

    CPC classification number: H01L23/5386 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

    Abstract translation: 公开了一种提供具有双图案化金属层结构的SRAM位单元的方法。 实施例包括：经由第一图案化工艺提供字线结构，接地线结构，电力线结构或其组合; 并且经由第二图案化处理提供靠近所述字线结构，所述接地线结构，所述电力线结构或其组合的位线结构。实施例包括：提供作为所述字线结构的第一着陆焊盘，以及第二 着陆板作为地线结构; 以及提供所述第一着陆垫具有第一末端边缘和第一侧边缘，并且所述第二着陆垫具有第二末端边缘和第二侧边缘，其中所述第一侧边缘面向所述第二侧边缘。

    SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS
    5.
    发明申请
    SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS 有权
    连续非均匀RX FINFET标准电池的特殊构造

    公开(公告)号：US20160225763A1

    公开(公告)日：2016-08-04

    申请号：US15063563

    申请日：2016-03-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Navneet JAIN ,  Juhan KIM ,  Andy NGUYEN ,  Mahbub RASHED

    IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L29/08

    CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

    Abstract translation: 提供了用于使具有不同大小的扩散区域的两个电池邻接的方法以及所得到的装置。 实施例包括：通过在两个单元之间的边界处形成虚拟栅极来邻接具有第一漏极和源极扩散区域的第一单元和具有大于第一扩散区域的第二漏极和源极扩散区域的第二单元; 形成连续的漏极扩散区域，其具有与伪栅极交叉的上部，并且包围整个第一漏极扩散区域和第二漏极扩散区域的一部分，并且具有从伪栅极开始的下部，并且包围第二漏极扩散区域的剩余部分 ; 形成作为连续漏极扩散区域的镜像的连续源极扩散区域; 以及在连续的漏极和源极扩散区之间在虚拟栅极之间形成多边形掩模，但是与连续的漏极和源极扩散区分离。

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