公开(公告)号：US20160225763A1

公开(公告)日：2016-08-04

申请号：US15063563

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet JAIN ,  Juhan KIM ,  Andy NGUYEN ,  Mahbub RASHED

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract translation: 提供了用于使具有不同大小的扩散区域的两个电池邻接的方法以及所得到的装置。 实施例包括：通过在两个单元之间的边界处形成虚拟栅极来邻接具有第一漏极和源极扩散区域的第一单元和具有大于第一扩散区域的第二漏极和源极扩散区域的第二单元; 形成连续的漏极扩散区域，其具有与伪栅极交叉的上部，并且包围整个第一漏极扩散区域和第二漏极扩散区域的一部分，并且具有从伪栅极开始的下部，并且包围第二漏极扩散区域的剩余部分 ; 形成作为连续漏极扩散区域的镜像的连续源极扩散区域; 以及在连续的漏极和源极扩散区之间在虚拟栅极之间形成多边形掩模，但是与连续的漏极和源极扩散区分离。

公开(公告)号：US20140346662A1

公开(公告)日：2014-11-27

申请号：US13902395

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub RASHED ,  Lei YUAN

IPC: G06F17/50 ,  H01L29/78 ,  H01L29/66

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  Y02T10/82

Abstract: Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder.

Abstract translation: 公开了用于容纳用于半导体单元的单元高度的M2间距的非整数倍的方法以及所得到的器件。 实施例可以包括在具有第一整数和余数乘以金属轨道层的轨道间距的集成电路（IC）内形成单元，以及在金属轨道层的边界处形成用于为 余。

公开(公告)号：US20180122804A1

公开(公告)日：2018-05-03

申请号：US15857202

申请日：2017-12-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet JAIN ,  Juhan KIM ,  Andy NGUYEN ,  Mahbub RASHED

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US20150052494A1

公开(公告)日：2015-02-19

申请号：US13968850

申请日：2013-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc TARABBIA ,  Norman CHEN ,  Jian LIU ,  Nader Magdy HINDAWY ,  Tuhin Guha NEOGI ,  Mahbub RASHED ,  Anurag MITTAL

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/06 ,  G06F2217/78

Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.

Abstract translation: 一种方法包括将标准单元库的多个单元电连接到电源轨。 沉积接触区以连接多个单元的单元的第一有源区和第二有源区。 第一区域和第二区域位于轨道的相对侧并且电连接到不同的排水沟。 接触区域使用通孔电连接到电源轨。 接触区域被屏蔽以去除接触区域的一部分以将第一活性物质与第二活性区域电分离。

公开(公告)号：US20140332967A1

公开(公告)日：2014-11-13

申请号：US14337596

申请日：2014-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juhan KIM ,  Mahbub RASHED

IPC: H01L23/538 ,  H01L27/11

CPC classification number: H01L23/5386 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

Abstract translation: 公开了一种提供具有双图案化金属层结构的SRAM位单元的方法。 实施例包括：经由第一图案化工艺提供字线结构，接地线结构，电力线结构或其组合; 并且经由第二图案化处理提供靠近所述字线结构，所述接地线结构，所述电力线结构或其组合的位线结构。实施例包括：提供作为所述字线结构的第一着陆焊盘，以及第二 着陆板作为地线结构; 以及提供所述第一着陆垫具有第一末端边缘和第一侧边缘，并且所述第二着陆垫具有第二末端边缘和第二侧边缘，其中所述第一侧边缘面向所述第二侧边缘。

公开(公告)号：US20180315708A1

公开(公告)日：2018-11-01

申请号：US15583449

申请日：2017-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anurag MITTAL ,  Mahbub RASHED

IPC: H01L23/528 ,  H01L29/45 ,  H01L29/08 ,  H01L27/12 ,  H01L23/532 ,  H01L23/522

Abstract: An electrical connection is provided between a source/drain of a planar transistor and a local interconnect or first metallization layer power rail, includes a first contact area electrically coupled to the source/drain, a second contact area electrically coupled to the first contact area and a gate of the transistor, and a V0 electrically coupled to the local interconnect or first metallization layer power rail. Trench silicide is absent from the transistor. A contact area-based power rail spine is also provided including a first contact area, a second contact area and adjacent V0 bi-directional staple both over and electrically coupled to the first contact area, and a V0 over and electrically coupled to the second contact area and the V0 bi-directional staple. The power rail spine may be included in a semiconductor structure including planar transistors, in which the first contact area and second contact area are electrically coupled to a source/drain of a transistor, a via-type gate contact is also electrically coupled to the second contact area under the V0. The first metallization layer and/or the contact areas may be made of a non-copper heavy metal with a minimum area less than that of copper.

公开(公告)号：US20160322367A1

公开(公告)日：2016-11-03

申请号：US15140548

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juhan KIM ,  Mahbub RASHED

IPC: H01L27/11 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

Abstract translation: 公开了一种用于提供具有小型化位单元的SRAM位单元的方法，没有本地互连层，具有改进的平版印刷可印刷性和使能方法。 实施例包括在M1层中提供包括第一字线，第一位线，第二位线，第一接地线，第二接地线，第二锁存线或其组合的第一颜色结构，其中第一 颜色结构包括比边缘长的侧边缘; 在M1层中提供第二颜色结构，包括第二字线，第一电源线，第二电源线，第一锁存线或其组合，其中第二颜色结构包括比尖端边缘长的侧边缘; 以及形成包括所述第一颜色结构和所述第二颜色结构的位单元，其中相邻的尖端边缘包括第一颜色结构的尖端边缘和第二颜色结构的尖端边缘。

公开(公告)号：US20160117432A1

公开(公告)日：2016-04-28

申请号：US14523558

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Irene LIN ,  Jongwook KYE ,  Mahbub RASHED

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A method and apparatus for an assisted metal routing is disclosed. Embodiments may include: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; and determining a modified block mask based on the assistant metal portion for forming the metal routing layer.

Abstract translation: 公开了一种用于辅助金属布线的方法和装置。 实施例可以包括：确定具有用于形成集成电路（IC）的金属布线层的第一内部顶点的初始块掩模; 在所述金属布线层内添加辅助金属部分; 以及基于用于形成金属布线层的辅助金属部分确定修改的块掩模。

公开(公告)号：US20150213184A1

公开(公告)日：2015-07-30

申请号：US14163511

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Mahbub RASHED ,  Jongwook KYE

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  Y02T10/82

Abstract: A methodology for a modified cell architecture and the resulting devices are disclosed. Embodiments may include determining a first vertical track spacing for a plurality of first routes for an integrated circuit (IC) design, each of the plurality of first routes having a first width, determining a second vertical track spacing for a second route for the IC design, the second route having a second width, and designating a cell vertical dimension for the IC design based on the first and second vertical track spacings.

Abstract translation: 公开了修改的小区体系结构的方法以及所得到的设备。 实施例可以包括确定用于集成电路（IC）设计的多个第一路由的第一垂直轨道间隔，所述多个第一路线中的​​每一条路径具有第一宽度，确定用于IC设计的第二路线的第二垂直轨道间距 所述第二路径具有第二宽度，并且基于所述第一和第二垂直轨道间隔指定所述IC设计的单元垂直尺寸。

公开(公告)号：US20190267801A1

公开(公告)日：2019-08-29

申请号：US15906475

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil KUMAR ,  Manjunatha G. PRABHU ,  Alain F. LOISEAU ,  Mahbub RASHED ,  Sushama DAVAR

IPC: H02H9/04 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.