公开(公告)号：US20200295017A1

公开(公告)日：2020-09-17

申请号：US16298413

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien FROUGIER ,  Ruilong XIE

IPC: H01L27/11514 ,  H01L49/02 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode.

公开(公告)号：US20200058757A1

公开(公告)日：2020-02-20

申请号：US16105102

申请日：2018-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Chanro PARK ,  Julien FROUGIER ,  Kangguo CHENG ,  Andre P. LABONTE

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.

公开(公告)号：US20200212192A1

公开(公告)日：2020-07-02

申请号：US16238173

申请日：2019-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Julien FROUGIER ,  Chanro PARK ,  Kangguo CHENG

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L23/535 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

Abstract: A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region.

公开(公告)号：US20200119180A1

公开(公告)日：2020-04-16

申请号：US16160701

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien FROUGIER ,  Ruilong XIE

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.