公开(公告)号：US20170352661A1

公开(公告)日：2017-12-07

申请号：US15174273

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo CHENG ,  Carl J. RADENS

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/7848

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finFET structures and methods of manufacture. The structure includes at least one logic finFET device having a fin of a first length, and at least one memory finFET device having a fin of a second length. The second length is shorter than the first length.

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20180158967A1

公开(公告)日：2018-06-07

申请号：US15886927

申请日：2018-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao LI ,  Kangguo CHENG ,  Chengwen PEI ,  Geng WANG ,  Joseph ERVIN

IPC: H01L31/0232 ,  G02B6/42 ,  H01L23/48 ,  G02B6/122 ,  H01L31/02 ,  G02B6/12

CPC classification number: H01L31/02327 ,  G02B6/122 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12123 ,  H01L21/76898 ,  H01L23/481 ,  H01L31/02005

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

公开(公告)号：US20180047727A1

公开(公告)日：2018-02-15

申请号：US15234762

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charan V. SURISETTY ,  Dominic J. SCHEPIS ,  Kangguo CHENG ,  Alexander REZNICEK

IPC: H01L27/088 ,  H01L21/3105 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791

Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.

公开(公告)号：US20160190304A1

公开(公告)日：2016-06-30

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre MORIN ,  Kangguo CHENG ,  Jody FRONHEISER ,  Xiuyu CAI ,  Juntao LI ,  Shogo MOCHIZUKI ,  Ruilong XIE ,  Hong HE ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7849

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

Abstract translation: 具有基本上无缺陷的SiGe应变松弛缓冲层的改性硅衬底适用于构建高性能CMOS FinFET器件的基础。 可以通过切割或分割应变的外延膜来形成基本上无缺陷的SiGe应变松弛缓冲层，使得薄膜段的边缘经历弹性应变弛豫。 当片段足够小时，整个膜被松弛，使得膜基本上没有位错缺陷。 一旦形成了基本上无缺陷的应变松弛缓冲层，则可以从松弛的SRB层外延生长应变通道层。 然后将应变通道层图案化以产生用于FinFET器件的鳍片。 在一个实施例中，形成双应变通道层 - 用于NFET器件的拉伸应变层，以及用于PFET器件的压缩应变层。

公开(公告)号：US20200212192A1

公开(公告)日：2020-07-02

申请号：US16238173

申请日：2019-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Julien FROUGIER ,  Chanro PARK ,  Kangguo CHENG

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L23/535 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

Abstract: A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region.

公开(公告)号：US20180090598A1

公开(公告)日：2018-03-29

申请号：US15280451

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Tenko YAMASHITA ,  Kangguo CHENG ,  Chun-Chen YEH

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L21/033 ,  H01L27/088

CPC classification number: H01L29/66666 ,  H01L21/0332 ,  H01L21/0337 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66545 ,  H01L29/7827

Abstract: A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height. The method further includes forming a top source/drain layer over the vertical channel, replacing the dummy gate with a metal gate, and forming self-aligned source, drain and gate contacts.

公开(公告)号：US20170330934A1

公开(公告)日：2017-11-16

申请号：US15155761

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John ZHANG ,  Lawrence CLEVENGER ,  Kangguo CHENG ,  Balasubramanian HARAN

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/0665 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.

公开(公告)号：US20160163826A1

公开(公告)日：2016-06-09

申请号：US14564323

申请日：2014-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Alexander REZNICEK ,  Dominic J. SCHEPIS

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct contact with the fin spacers such that a top surface of the fin and a top surface of the fin spacers remain exposed, recessing a portion of the fin between the fin spacers, removing the fin spacers to create an opening, and epitaxially growing an unmerged source drain region in the opening, where lateral growth of the unmerged source drain region is constrained on opposite sides by the dielectric layer.

Abstract translation: 一种方法，包括在由半导体衬底制成的半导体鳍片的相对侧壁上形成翅片间隔件，形成与翅片间隔件直接接触的电介质层，使得翅片的顶表面和翅片间隔件的顶表面保持暴露，凹陷 翅片间隔件的一部分，去除翅片间隔件以形成开口，并且在开口中外延生长未熔化的源极漏极区域，其中未熔化的源极漏极区域的横向生长通过电介质层约束在相对的两侧。

公开(公告)号：US20150024572A1

公开(公告)日：2015-01-22

申请号：US13945445

申请日：2013-07-18

Applicant: INTERNATIONAL BUSINESS MACHIES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Ajey P. JACOB ,  Kangguo CHENG ,  Bruce B. DORIS ,  Nicolas LOUBET ,  Prasanna KHARE ,  Ramachandra DIVAKARUNI

IPC: H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/302 ,  H01L21/76267 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1211 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了半导体制造方法，其包括：通过以下方式制造半导体鳍片结构：提供具有在衬底上延伸的至少一个翅片的晶片，所述至少一个鳍片包括设置在第二层上方的第一层; 机械稳定第一层; 去除所述翅片的所述第二层的至少一部分以在所述第一层下面形成空隙; 至少部分地用隔离材料填充第一层下面的空隙，以在散热片内产生隔离层; 并且在翅片的第一翅片区域中形成第一结构类型的翅片装置，并且在翅片的第二翅片区域中形成第二结构类型的翅片装置， ，其中第一种架构类型和第二种架构类型是不同的鳍设备架构。