公开(公告)号：US09147680B2

公开(公告)日：2015-09-29

申请号：US13943944

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Abstract translation: 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成斜面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US20150021694A1

公开(公告)日：2015-01-22

申请号：US13943944

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Abstract translation: 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成倒角表面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US09252238B1

公开(公告)日：2016-02-02

申请号：US14461887

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Liu ,  Gabriel Padron Wells ,  Xing Zhang ,  Hoong Shing Wong ,  Chang Ho Maeng ,  Taejoon Han ,  Gowri Kamarthy ,  Isabelle Orain ,  Ganesh Upadhyaya

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract translation: 提供半导体结构和制造方法，其包括例如在半导体衬底上提供栅极结构，所述栅极结构包括多个共形栅极层和设置在多个共形栅极层内的栅极材料; 将多个共形栅极层的一部分凹陷在栅极结构的上表面之下，其中凹入的多个共形栅极层的上表面是共面的; 以及去除所述栅极材料的一部分以便于所述栅极材料的剩余部分的上表面与所述凹入的多个共形栅极层的上表面共面。