公开(公告)号：US20180047738A1

公开(公告)日：2018-02-15

申请号：US15234066

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Krottenthaler ,  Martin Mazur

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/161 ,  H01L27/12 ,  H01L29/788

CPC classification number: H01L27/11546 ,  H01L27/1207 ,  H01L29/161 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

公开(公告)号：US09972634B2

公开(公告)日：2018-05-15

申请号：US15234066

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Krottenthaler ,  Martin Mazur

IPC: H01L27/115 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L27/11546 ,  H01L27/1207 ,  H01L29/161 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

公开(公告)号：US09372392B2

公开(公告)日：2016-06-21

申请号：US14325515

申请日：2014-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Martin Mazur ,  Dietmar Henke ,  Hans-Juergen Thees

IPC: G03F1/22 ,  G03F1/24 ,  G03F7/20 ,  G03F1/00

CPC classification number: G03F1/24 ,  G03F1/22 ,  G03F1/50 ,  G03F7/2026 ,  G03F7/2045

Abstract: In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.

Abstract translation: 在一个示例中，本文公开的掩模版包括具有中心的主体，多个曝光图案的布置，其中该布置的中心偏离主体的中心，以及限定在该主体上或之上的至少一个开放特征 标线的主体。 在另一个实例中，公开了一种方法，其包括在多个功能模具上形成光致抗蚀剂层和多个不完全模具，使位于功能模具中的至少一个上的光致抗蚀剂材料和/或至少一个不完全模具 通过掩模版的开放特征执行不完全的裸片曝光处理，以露出位于多个不完全裸片上方的基本上所有的光致抗蚀剂材料，并且显影光致抗蚀剂以去除位于不完全裸片上方的光刻胶材料的部分。

公开(公告)号：US20140329173A1

公开(公告)日：2014-11-06

申请号：US14325515

申请日：2014-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Martin Mazur ,  Dietmar Henke ,  Hans-Juergen Thees

IPC: G03F1/22 ,  G03F1/00

CPC classification number: G03F1/24 ,  G03F1/22 ,  G03F1/50 ,  G03F7/2026 ,  G03F7/2045

Abstract: In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.