Abstract:
Methods for enabling in-line detection of TS-PC short defects at the TS-CMP processing stage are provided. Embodiments include providing a semiconductor substrate, the substrate having a plurality of partially formed MOSFET devices; performing a first defect inspection on the substrate, the first inspection including ACC; identifying one or more BVC candidates on the substrate based on the first inspection; performing a second defect inspection on the one or more BVC candidates, the second inspection performed without ACC; and detecting one or more BVC defects on the substrate based on the one or more BVC candidates appearing during both the first and second inspections.
Abstract:
A method and apparatus for detecting VC defects and determining the exact shorting locations based on charging dynamics induced by scan direction variation are provided. Embodiments include providing a substrate having at least a partially formed device thereon, the partially formed device having at least a word-line, a share contact, and a bit-line; performing a first EBI on the at least partially formed device in a single direction; classifying defects by ADC based on the first EBI inspection; selecting DOI among the classified defects for further review; performing a second EBI on the DOI in a first, second, third, and fourth direction; comparing a result of the first direction against a result of the second direction and/or a result of the third direction against a result of the fourth direction; and determining a shorting location for each DOI based on the one or more comparisons.