公开(公告)号：US20180197882A1

公开(公告)日：2018-07-12

申请号：US15912141

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David PRITCHARD ,  Lixia LEI ,  Deniz E. CIVAY ,  Scott D. LUNING ,  Neha NAYYAR

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/84 ,  H01L29/40

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/7838

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.

公开(公告)号：US20200058515A1

公开(公告)日：2020-02-20

申请号：US16662091

申请日：2019-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng YANG ,  David C. PRITCHARD ,  George J. KLUTH ,  Anurag MITTAL ,  Hongru REN ,  Manjunatha G. PRABHU ,  Kai SUN ,  Neha NAYYAR ,  Lixia LEI

IPC: H01L21/308 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

公开(公告)号：US20190012422A1

公开(公告)日：2019-01-10

申请号：US15644288

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Neha NAYYAR ,  Daniel J. DECHENE ,  David C. PRITCHARD ,  George J. KLUTH

IPC: G06F17/50 ,  H01L23/522

Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.