公开(公告)号：US20200058515A1

公开(公告)日：2020-02-20

申请号：US16662091

申请日：2019-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng YANG ,  David C. PRITCHARD ,  George J. KLUTH ,  Anurag MITTAL ,  Hongru REN ,  Manjunatha G. PRABHU ,  Kai SUN ,  Neha NAYYAR ,  Lixia LEI

IPC: H01L21/308 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

公开(公告)号：US20180197882A1

公开(公告)日：2018-07-12

申请号：US15912141

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David PRITCHARD ,  Lixia LEI ,  Deniz E. CIVAY ,  Scott D. LUNING ,  Neha NAYYAR

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/84 ,  H01L29/40

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/7838

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.

公开(公告)号：US20150287604A1

公开(公告)日：2015-10-08

申请号：US14246197

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason E. STEPHENS ,  Lei YUAN ,  Lixia LEI ,  David PRITCHARD ,  Tuhin Guha NEOGI

IPC: H01L21/28

CPC classification number: H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.

Abstract translation: 提供了一种用于在晶片上制造交叉耦合线段以用于例如制造两个或多个晶体管的交叉耦合栅极的方法。 该制造包括：使用第一掩模使具有第一侧面突起的第一线段图案化; 以及使用第二掩模用第二侧面突起构图第二线段。 第二线段与第一线段偏移，并且图案化的第二侧突起覆盖图案化的第一侧突起，并且有助于限定连接第一和第二线段的十字绣线段。 该方法还包括在限定来自第一和第二线段和十字绣段的交叉耦合线段时选择性地切割第一和第二线段。