公开(公告)号：US20200127013A1

公开(公告)日：2020-04-23

申请号：US16168414

申请日：2018-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David PRITCHARD ,  Heng YANG ,  Hongru REN

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L29/66 ,  H01L21/027 ,  H01L21/762

Abstract: The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.

公开(公告)号：US20200058515A1

公开(公告)日：2020-02-20

申请号：US16662091

申请日：2019-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng YANG ,  David C. PRITCHARD ,  George J. KLUTH ,  Anurag MITTAL ,  Hongru REN ,  Manjunatha G. PRABHU ,  Kai SUN ,  Neha NAYYAR ,  Lixia LEI

IPC: H01L21/308 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

公开(公告)号：US20180261456A1

公开(公告)日：2018-09-13

申请号：US15456757

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng YANG ,  Ahmed HASSAN ,  Daniel DECHENE

IPC: H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/76885 ,  H01L29/66545

Abstract: A single critical mask process flow and associated structure eliminate the formation of narrow polysilicon defects at the ends of polysilicon gate arrays, and obviate the need to implement complicated ground rules and post-design fill methods to avoid generation of the defects.