公开(公告)号：US09269607B2

公开(公告)日：2016-02-23

申请号：US14306598

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edward Engbrecht ,  Donghun Kang ,  Rishikesh Krishnan ,  Oh-jung Kwon ,  Karen A. Nummy

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/308 ,  H01L21/321 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L21/76227 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3212 ,  H01L22/12 ,  H01L29/0603 ,  H01L29/945

Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

Abstract translation: 本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。 诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。 在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片前侧上的电功能DT。 在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。 通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。 这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。